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      <base href="https://bugs.llvm.org/">
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    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - [MCA][CodeGenSchedule] Better handling of instructions with zero NumMicroOpcodes."
   href="https://bugs.llvm.org/show_bug.cgi?id=44797">44797</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>[MCA][CodeGenSchedule] Better handling of instructions with zero NumMicroOpcodes.
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>tools
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>Windows NT
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>enhancement
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>llvm-mca
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>andrea.dibiagio@gmail.com
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>andrea.dibiagio@gmail.com, llvm-bugs@lists.llvm.org, matthew.davis@sony.com
          </td>
        </tr></table>
      <p>
        <div>
        <pre>Field NumMicroOpcodes is currently used by mca to model the number of uOPs
dispatched from the uOp-Queue to the out of order backend.
>From a 'dispatch' point of view, an instruction with zero opcodes is still
valid; it simply doesn't consume any dispatch group slots.

However, mca doesn't expect an instruction with zero uOPs to consume pipeline
resources because it is seen as a contradiction.
In practice, it only makes sense if the instruction is eliminated and never
really executed. It may be that mca is being too conservative here. However I
believe that mca is right, and we should probably check that inconsistency in
CodeGenSchedule.cpp (when we also verify scheduling classes in general).

In the short term I plan to remove the check for MayLoad and MayStore in mca.
That check is probably too conservative: we already check if a zero-uops
instruction consumes any processor resources. Also, instructions with
unmodelled side-effects tend to also set the MayLoad/MayStore flags even if -
theoretically speaking - they might not even consume any hw resources in
practice.

In future we may want to implement different checks (possibly outside of mca)
and potentially revisit the logic in mca that verifies instructions.</pre>
        </div>
      </p>


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