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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [MSP430][AVR][InstCombine][DAGCombine]Poor codegen for targets with no native shifts (3/8)"
href="https://bugs.llvm.org/show_bug.cgi?id=44040">44040</a>
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<th>Summary</th>
<td>[MSP430][AVR][InstCombine][DAGCombine]Poor codegen for targets with no native shifts (3/8)
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
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<th>Hardware</th>
<td>All
</td>
</tr>
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<th>OS</th>
<td>All
</td>
</tr>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>normal
</td>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>Common Code Generator Code
</td>
</tr>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
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<th>Reporter</th>
<td>joan.lluch@icloud.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
</tr></table>
<p>
<div>
<pre>A number of comparisons involving bit tests are converted into shifts by
InstCombine and DAGCombine. However, shifts are expensive for most 8 and 16 bit
targets with comparatively cheaper selects.
It is desirable that selects are emitted instead of shifts for these targets.
The following cases were identified in TargetLowering and DAGCombine and were
fixed by:
<a href="https://reviews.llvm.org/D69116">https://reviews.llvm.org/D69116</a>
<a href="https://reviews.llvm.org/D69120">https://reviews.llvm.org/D69120</a>
<a href="https://reviews.llvm.org/D69326">https://reviews.llvm.org/D69326</a>
<a href="https://reviews.llvm.org/D70042">https://reviews.llvm.org/D70042</a>
Cases in InstCombine remain to be fixed. In llvm-dev it has been suggested that
these cases should be fixed by reversing the current canonicalisation. I am
showing them in this and following reports:
REPORTED CASE:
Source code:
int testExtendSignBit_0( int x ) // (InstCombineCasts::transformSExtICmp)
{
return x<0 ? 0 : -1;
}
IR code:
define i16 @testExtendSignBit_0(i16 %x) {
entry:
%x.lobit = ashr i16 %x, 15
%x.lobit.not = xor i16 %x.lobit, -1
ret i16 %x.lobit.not
}
MSP430 Target code:
testExtendSignBit_0:
swpb r12
sxt r12
rra r12
rra r12
rra r12
rra r12
rra r12
rra r12
rra r12
inv r12
ret
AVR Target code:
testExtendSignBit_0:
asr r25
ror r24
asr r25
ror r24
asr r25
ror r24
asr r25
ror r24
asr r25
ror r24
asr r25
ror r24
asr r25
ror r24
asr r25
ror r24
asr r25
ror r24
asr r25
ror r24
asr r25
ror r24
asr r25
ror r24
asr r25
ror r24
asr r25
ror r24
asr r25
ror r24
com r24
com r25
ret
EXPECTED RESULT:
Source code:
int testExtendSignBit_0( int x ) // (InstCombineCasts::transformSExtICmp)
{
return x<0 ? 0 : -1;
}
Expected IR code:
define i16 @testExtendSignBit_0(i16 %x) {
entry:
%cmp = icmp sgt i16 %x, -1
%cond = sext i1 %cmp to i16
ret i16 %cond
}
Expected MSP430 Target code:
testExtendSignBit_0:
mov r12, r13
mov #-1, r12
tst r13
jge .LBB2_2
clr r12
.LBB2_2:
ret
Expected AVR Target code:
testExtendSignBit_0:
tst r25
brpl LBB2_2
ldi r24, 0
ldi r25, 0
ret
LBB2_2:
ldi r24, 255
ldi r25, 255
ret</pre>
</div>
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