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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - Invalid Hexagon disassembly with new-value operands"
href="https://bugs.llvm.org/show_bug.cgi?id=43867">43867</a>
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<th>Summary</th>
<td>Invalid Hexagon disassembly with new-value operands
</td>
</tr>
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<th>Product</th>
<td>new-bugs
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Linux
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>new bugs
</td>
</tr>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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</tr>
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<th>Reporter</th>
<td>w.parker.thompson@gmail.com
</td>
</tr>
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<th>CC</th>
<td>htmldeveloper@gmail.com, llvm-bugs@lists.llvm.org
</td>
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<p>
<div>
<pre>Reproduction:
echo "0x01, 0x43, 0x1d, 0xb0, 0x92, 0x43, 0x00, 0x00, 0x00, 0x43, 0x00, 0x78,
0x01, 0xd5, 0xbd, 0xa1" | llvm-mc -disassemble -triple=hexagon
Result:
<stdin>:1:1: warning: invalid instruction encoding
0x01, 0x43, 0x1d, 0xb0, 0x92, 0x43, 0x00, 0x00, 0x00, 0x43, 0x00, 0x78, 0x01,
0xd5, 0xbd, 0xa1
Expected disassembly:
{
r1 = add(r29,#24)
r0 = ##58520
memw(r29+#4) = r1.new
}
Possible cause (speculation):
The bug appears to be at:
<a href="https://github.com/llvm/llvm-project/blob/a678677da498a45f59c16ee74fea438e34a801ce/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp#L488">https://github.com/llvm/llvm-project/blob/a678677da498a45f59c16ee74fea438e34a801ce/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp#L488</a>
The disassembler fetches the register enum value and not the Nt bits from the
instruction itself (location varies by instruction). This means when the
SubregBit is checked, it will fail the check at line:
<a href="https://github.com/llvm/llvm-project/blob/a678677da498a45f59c16ee74fea438e34a801ce/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp#L501">https://github.com/llvm/llvm-project/blob/a678677da498a45f59c16ee74fea438e34a801ce/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp#L501</a>
for every odd register (like the example above).</pre>
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