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<base href="https://bugs.llvm.org/">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - X86TargetLowering::LowerTRUNCATE(llvm::SDValue, llvm::SelectionDAG &) const: Assertion `VT.is128BitVector() && InVT.is256BitVector() && "Unexpected types!"' failed."
href="https://bugs.llvm.org/show_bug.cgi?id=42905">42905</a>
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<th>Summary</th>
<td>X86TargetLowering::LowerTRUNCATE(llvm::SDValue, llvm::SelectionDAG &) const: Assertion `VT.is128BitVector() && InVT.is256BitVector() && "Unexpected types!"' failed.
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
<tr>
<th>OS</th>
<td>Linux
</td>
</tr>
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<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>enhancement
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Backend: X86
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>bjorn.a.pettersson@ericsson.com
</td>
</tr>
<tr>
<th>CC</th>
<td>craig.topper@gmail.com, llvm-bugs@lists.llvm.org, llvm-dev@redking.me.uk, spatel+llvm@rotateright.com
</td>
</tr></table>
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<div>
<pre>Created <span class=""><a href="attachment.cgi?id=22346" name="attach_22346" title="reproducer (can probably be reduced further)">attachment 22346</a> <a href="attachment.cgi?id=22346&action=edit" title="reproducer (can probably be reduced further)">[details]</a></span>
reproducer (can probably be reduced further)
When running
llc -march=x86-64 -mcpu=corei7 -o /dev/null stress-size-300-seed-30452.ll
we hit an assertion in X86TargetLowering::LowerTRUNCATE
llc: ../lib/Target/X86/X86ISelLowering.cpp:19161: llvm::SDValue
llvm::X86TargetLowering::LowerTRUNCATE(llvm::SDValue, llvm::SelectionDAG &)
const: Assertion `VT.is128BitVector() && InVT.is256BitVector() && "Unexpected
types!"' failed.
Stack dump:
0. Program arguments: bin/llc -march=x86-64 -mcpu=corei7 -o /dev/null
stress.ll -x86-experimental-vector-widening-legalization=1
1. Running pass 'Function Pass Manager' on module 'stress.ll'.
2. Running pass 'X86 DAG->DAG Instruction Selection' on function
'@autogen_SD30452'
#0 0x0000000002345914 PrintStackTraceSignalHandler(void*) (bin/llc+0x2345914)
#1 0x00000000023435fe llvm::sys::RunSignalHandlers() (bin/llc+0x23435fe)
#2 0x0000000002345d18 SignalHandler(int) (bin/llc+0x2345d18)
#3 0x0000003ba280f7e0 __restore_rt (/lib64/libpthread.so.0+0x3ba280f7e0)
#4 0x0000003ba24324f5 raise (/lib64/libc.so.6+0x3ba24324f5)
#5 0x0000003ba2433cd5 abort (/lib64/libc.so.6+0x3ba2433cd5)
#6 0x0000003ba242b66e __assert_fail_base (/lib64/libc.so.6+0x3ba242b66e)
#7 0x0000003ba242b730 __assert_perror_fail (/lib64/libc.so.6+0x3ba242b730)
#8 0x0000000001255826 llvm::X86TargetLowering::LowerTRUNCATE(llvm::SDValue,
llvm::SelectionDAG&) const (bin/llc+0x1255826)
#9 0x0000000001270c63 llvm::X86TargetLowering::LowerOperation(llvm::SDValue,
llvm::SelectionDAG&) const (bin/llc+0x1270c63)
#10 0x000000000222cb44 (anonymous
namespace)::VectorLegalizer::LegalizeOp(llvm::SDValue) (bin/llc+0x222cb44)
#11 0x000000000222b31e llvm::SelectionDAG::LegalizeVectors()
(bin/llc+0x222b31e)
#12 0x00000000021c6f38 llvm::SelectionDAGISel::CodeGenAndEmitDAG()
(bin/llc+0x21c6f38)
#13 0x00000000021c581c
llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&)
(bin/llc+0x21c581c)
#14 0x00000000021c21b6
llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&)
(bin/llc+0x21c21b6)
#15 0x0000000001210bf6 (anonymous
namespace)::X86DAGToDAGISel::runOnMachineFunction(llvm::MachineFunction&)
(bin/llc+0x1210bf6)
#16 0x000000000197d919
llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (bin/llc+0x197d919)
#17 0x0000000001cec553 llvm::FPPassManager::runOnFunction(llvm::Function&)
(bin/llc+0x1cec553)
#18 0x0000000001cec863 llvm::FPPassManager::runOnModule(llvm::Module&)
(bin/llc+0x1cec863)
#19 0x0000000001cececd llvm::legacy::PassManagerImpl::run(llvm::Module&)
(bin/llc+0x1cececd)
#20 0x00000000007890ce compileModule(char**, llvm::LLVMContext&)
(bin/llc+0x7890ce)
#21 0x000000000078682d main (bin/llc+0x78682d)
#22 0x0000003ba241ed20 __libc_start_main (/lib64/libc.so.6+0x3ba241ed20)
#23 0x00000000007844c9 _start (bin/llc+0x7844c9)
Abort (core dumped)
This problem turned up after -x86-experimental-vector-widening-legalization was
set to true by default in this commit:
commit 3de33245d2c992c9e0af60372043540b60f3a810
Author: Craig Topper <<a href="mailto:craig.topper@intel.com">craig.topper@intel.com</a>>
Date: Mon Aug 5 18:25:36 2019 +0000
[X86] Enable -x86-experimental-vector-widening-legalization by default.
This patch changes our defualt legalization behavior for 16, 32, and
64 bit vectors with i8/i16/i32/i64 scalar types from promotion to
widening. For example, v8i8 will now be widened to v16i8 instead of
promoted to v8i16. This keeps the elements widths the same and pads
with undef elements. We believe this is a better legalization strategy.
But it carries some issues due to the fragmented vector ISA. For
example, i8 shifts and multiplies get widened and then later have
to be promoted/split into vXi16 vectors.
This has the potential to cause regressions so we wanted to get
it in early in the 10.0 cycle so we have plenty of time to
address them.
Next steps will be to merge tests that explicitly test the command
line option. And then we can remove the option and its associated
code.
llvm-svn: 367901
Adding -debug gives the following DAG being legalized when hitting the assert:
Optimized type-legalized selection DAG: %bb.24 'autogen_SD30452:CF259'
SelectionDAG has 35 nodes:
t0: ch = EntryToken
t32: v2i64,ch = CopyFromReg t0, Register:v2i64 %8
t49: ch = CopyToReg t0, Register:f32 %110, ConstantFP:f32<8.193822e+16>
t55: i8,ch = CopyFromReg t0, Register:i8 %22
t51: i64,ch = CopyFromReg t0, Register:i64 %135
t56: ch = store<(store 1 into %ir.0)> t0, t55, t51, undef:i64
t68: v2f64 = sint_to_fp t32
t42: ch = CopyToReg t0, Register:v2f64 %108, t68
t34: v2i64,ch = CopyFromReg t32:1, Register:v2i64 %9
t35: v2i64 = AssertZext t34, ValueType:ch:i18
t78: v2i32 = truncate t35
t79: v2f64 = sint_to_fp t78
t44: ch = CopyToReg t0, Register:v2f64 %109, t79
t67: ch = TokenFactor t49, t56, t42, t44
t58: v4i32,ch = CopyFromReg t0, Register:v4i32 %93
t75: v16i8 = bitcast t58
t77: i8 = extract_vector_elt t75, Constant:i64<8>
t74: i8 = and t77, Constant:i8<1>
t64: ch = brcond t67, t74, BasicBlock:ch<CF242 0x579b298>
t66: ch = br t64, BasicBlock:ch<CF245.preheader 0x579b428>
Legalizing vector op: t78: v2i32 = truncate t35
Trying custom legalization
llc: ../lib/Target/X86/X86ISelLowering.cpp:19161: llvm::SDValue
llvm::X86TargetLowering::LowerTRUNCATE(llvm::SDValue, llvm::SelectionDAG &)
const: Assertion `VT.is128BitVector() && InVT.is256BitVector() && "Unexpected
types!"' failed.</pre>
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