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<body><span class="vcard"><a class="email" href="mailto:nicolasweber@gmx.de" title="Nico Weber <nicolasweber@gmx.de>"> <span class="fn">Nico Weber</span></a>
</span> changed
<a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - Assertion failed: isValidGCCRegisterName(Name) && "Invalid register passed in", file E:\llvm\tools\clang\lib\Basic\Targe tInfo.cpp, line 415"
href="https://bugs.llvm.org/show_bug.cgi?id=30930">bug 30930</a>
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<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>What</th>
<th>Removed</th>
<th>Added</th>
</tr>
<tr>
<td style="text-align:right;">Resolution</td>
<td>---
</td>
<td>FIXED
</td>
</tr>
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<td style="text-align:right;">Status</td>
<td>NEW
</td>
<td>RESOLVED
</td>
</tr>
<tr>
<td style="text-align:right;">CC</td>
<td>
</td>
<td>nicolasweber@gmx.de
</td>
</tr></table>
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<b><a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - Assertion failed: isValidGCCRegisterName(Name) && "Invalid register passed in", file E:\llvm\tools\clang\lib\Basic\Targe tInfo.cpp, line 415"
href="https://bugs.llvm.org/show_bug.cgi?id=30930#c1">Comment # 1</a>
on <a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - Assertion failed: isValidGCCRegisterName(Name) && "Invalid register passed in", file E:\llvm\tools\clang\lib\Basic\Targe tInfo.cpp, line 415"
href="https://bugs.llvm.org/show_bug.cgi?id=30930">bug 30930</a>
from <span class="vcard"><a class="email" href="mailto:nicolasweber@gmx.de" title="Nico Weber <nicolasweber@gmx.de>"> <span class="fn">Nico Weber</span></a>
</span></b>
<pre>This seems to work now:
$ cat test.c
void foo(void)
{
__asm mov cr2, eax;
}
$ out/gn/bin/clang-cl /c test.c
test.c(3,5): error: instruction requires: Not 64-bit mode
__asm mov cr2, eax;
^
<inline asm>(2,2): note: instantiated into assembly here
mov cr2, eax
^
1 error generated.
$ out/gn/bin/clang-cl /c test.c -m32
$ out/gn/bin/llvm-objdump --disassemble test.obj
test.obj: file format COFF-i386
Disassembly of section .text:
00000000 _foo:
0: 55 pushl %ebp
1: 89 e5 movl %esp, %ebp
3: 0f 22 d0 movl %eax, %cr2
6: 5d popl %ebp
7: c3 retl</pre>
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