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<base href="https://bugs.llvm.org/">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - Invalid register allocation for AVX512 gather"
href="https://bugs.llvm.org/show_bug.cgi?id=42055">42055</a>
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<th>Summary</th>
<td>Invalid register allocation for AVX512 gather
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Linux
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>normal
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>Backend: X86
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>benny.kra@gmail.com
</td>
</tr>
<tr>
<th>CC</th>
<td>craig.topper@gmail.com, llvm-bugs@lists.llvm.org, llvm-dev@redking.me.uk, spatel+llvm@rotateright.com
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<pre>Created <span class=""><a href="attachment.cgi?id=22042" name="attach_22042" title="reduced test case">attachment 22042</a> <a href="attachment.cgi?id=22042&action=edit" title="reduced test case">[details]</a></span>
reduced test case
While chasing a SIGILL I came across this. Intrinsics were generated by
LoopVectorizer. Manual says: "If any pair of the index, mask, or destination
registers are the same, this instruction results a UD fault."
$ cat t.ll
define void @reduced() #0 {
%wide.masked.gather38 = call <16 x float>
@llvm.masked.gather.v16f32.v16p0f32(<16 x float*> undef, i32 4, <16 x i1> <i1
true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1
false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>,
<16 x float> undef)
%1 = fadd fast <16 x float> %wide.masked.gather38, zeroinitializer
call void @llvm.masked.store.v16f32.p0v16f32(<16 x float> %1, <16 x float>*
undef, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 false,
i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false,
i1 false, i1 false>)
ret void
}
; Function Attrs: nounwind readonly
declare <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*>, i32
immarg, <16 x i1>, <16 x float>) #1
; Function Attrs: argmemonly nounwind
declare void @llvm.masked.store.v16f32.p0v16f32(<16 x float>, <16 x float>*,
i32 immarg, <16 x i1>) #2
attributes #0 = { "unsafe-fp-math"="true" }
attributes #1 = { nounwind readonly }
attributes #2 = { argmemonly nounwind }
$ llc -mcpu=skx < t.ll | llvm-mc
<stdin>:10:2: warning: index and destination registers should be distinct
vgatherqps (,%zmm0), %ymm0 {%k1}
^</pre>
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