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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [X86] Scalarize non-temporal vector stores with poor alignment"
href="https://bugs.llvm.org/show_bug.cgi?id=42026">42026</a>
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<th>Summary</th>
<td>[X86] Scalarize non-temporal vector stores with poor alignment
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<th>Product</th>
<td>libraries
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<th>Version</th>
<td>trunk
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<th>Hardware</th>
<td>PC
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<th>OS</th>
<td>Windows NT
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>enhancement
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: X86
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>llvm-dev@redking.me.uk
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<th>CC</th>
<td>andrea.dibiagio@gmail.com, craig.topper@gmail.com, llvm-bugs@lists.llvm.org, llvm-dev@redking.me.uk, spatel+llvm@rotateright.com
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<pre>This possibly could be a generic DAG expansion, but I'm making it X86
initially.
The SSE/AVX NT store operations require vector alignment, so if that isn't
possible we currently emit general unaligned load/stores.
Given the coder has gone to the trouble of declaring the ops as non-temporal,
its almost certainly going to be worthwhile scalarizing the ops and using
scalar NT stores to try and avoid cache pollution.
In most cases this will involve trying to use SSE2's MOVNTI i32/i64 op, but if
we have SSE4A we can try to keep on the SIMD unit with MOVNTSD/MOVNTSS.</pre>
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