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<base href="https://bugs.llvm.org/">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [WebAssembly] Assertion failure with fast-isel and cross-bb use of i128"
href="https://bugs.llvm.org/show_bug.cgi?id=41841">41841</a>
</td>
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<tr>
<th>Summary</th>
<td>[WebAssembly] Assertion failure with fast-isel and cross-bb use of i128
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>All
</td>
</tr>
<tr>
<th>OS</th>
<td>All
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>enhancement
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Backend: WebAssembly
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>nikita.ppv@gmail.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
</tr></table>
<p>
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<pre>Running
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown"
declare i128 @foo(i128)
define void @test(i1 %b) {
start:
%zext = zext i1 %b to i128
br label %next
next: ; preds = %start
%ret = call i128 @foo(i128 %zext)
ret void
}
through llc -O0 gives
llc: ../include/llvm/ADT/IndexedMap.h:46: typename llvm::IndexedMap<T,
ToIndexT>::StorageT::reference llvm::IndexedMap<T,
ToIndexT>::operator[](llvm::IndexedMap<T, ToIndexT>::IndexT) [with T =
std::pair<llvm::PointerUnion<const llvm::TargetRegisterClass*, const
llvm::RegisterBank*>, llvm::MachineOperand*>; ToIndexT =
llvm::VirtReg2IndexFunctor; typename llvm::IndexedMap<T,
ToIndexT>::StorageT::reference = std::pair<llvm::PointerUnion<const
llvm::TargetRegisterClass*, const llvm::RegisterBank*>,
llvm::MachineOperand*>&; llvm::IndexedMap<T, ToIndexT>::IndexT = unsigned int]:
Assertion `toIndex_(n) < storage_.size() && "index out of bounds!"' failed.
with trace
#4 0x00007ffff3ac4a2f in
llvm::IndexedMap<std::pair<llvm::PointerUnion<llvm::TargetRegisterClass const*,
llvm::RegisterBank const*>, llvm::MachineOperand*>,
llvm::VirtReg2IndexFunctor>::operator[] (this=0x55555566e368, n=2147483653)
at ../include/llvm/ADT/IndexedMap.h:46
#5 0x00007ffff3ac4732 in llvm::MachineRegisterInfo::getRegUseDefListHead (
this=0x55555566e350, RegNo=2147483653)
at ../include/llvm/CodeGen/MachineRegisterInfo.h:112
#6 0x00007ffff3ac2b4e in llvm::MachineRegisterInfo::addRegOperandToUseList (
this=0x55555566e350, MO=0x55555566ee20)
at ../lib/CodeGen/MachineRegisterInfo.cpp:267
#7 0x00007ffff3a05cec in llvm::MachineInstr::AddRegOperandsToUseLists (
this=0x55555566ecf8, MRI=...) at ../lib/CodeGen/MachineInstr.cpp:173
#8 0x00007ffff3962fee in llvm::ilist_traits<llvm::MachineInstr>::addNodeToList
(this=0x55555566e8a0, N=0x55555566ecf8)
at ../lib/CodeGen/MachineBasicBlock.cpp:111
#9 0x00007ffff17fa589 in
llvm::iplist_impl<llvm::simple_ilist<llvm::MachineInstr,
llvm::ilist_sentinel_tracking<true> >, llvm::ilist_traits<llvm::MachineInstr>
<span class="quote">>::insert (this=0x55555566e8a0, where=..., New=0x55555566ecf8)</span >
at ../include/llvm/ADT/ilist.h:227
#10 0x00007ffff17f6674 in llvm::MachineBasicBlock::insert (
this=0x55555566e890, I=..., MI=0x55555566ecf8)
at ../include/llvm/CodeGen/MachineBasicBlock.h:627
#11 0x00007ffff18244e0 in llvm::InstrEmitter::EmitMachineNode (
this=0x7fffffffc5f0, Node=0x555555675858, IsClone=false, IsCloned=false,
VRBaseMap=...) at ../lib/CodeGen/SelectionDAG/InstrEmitter.cpp:927
#12 0x00007ffff18d1c53 in llvm::InstrEmitter::EmitNode (this=0x7fffffffc5f0,
Node=0x555555675858, IsClone=false, IsCloned=false, VRBaseMap=...)
at ../lib/CodeGen/SelectionDAG/InstrEmitter.h:123
#13 0x00007ffff18f01d7 in llvm::ScheduleDAGSDNodes::<lambda(llvm::SDNode*,
bool, bool, llvm::DenseMap<llvm::SDValue, unsigned int,
llvm::DenseMapInfo<llvm::SDValue>, llvm::detail::DenseMapPair<llvm::SDValue,
unsigned int> >&)>::operator()(llvm::SDNode *, bool, bool,
llvm::DenseMap<llvm::SDValue, unsigned int, llvm::DenseMapInfo<llvm::SDValue>,
llvm::detail::DenseMapPair<llvm::SDValue, unsigned int> > &) const
(__closure=0x7fffffffc5a0, Node=0x555555675858, IsClone=false,
IsCloned=false, VRBaseMap=...)
at ../lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp:849
Passing -fast-isel=false avoids the assertion.</pre>
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