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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [X86] Support X86ISD::VPTERNLOG ternary logic on all SSE/AVX targets"
href="https://bugs.llvm.org/show_bug.cgi?id=41454">41454</a>
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<th>Summary</th>
<td>[X86] Support X86ISD::VPTERNLOG ternary logic on all SSE/AVX targets
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<th>Product</th>
<td>libraries
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
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<th>OS</th>
<td>Windows NT
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>enhancement
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: X86
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>llvm-dev@redking.me.uk
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<th>CC</th>
<td>andrea.dibiagio@gmail.com, craig.topper@gmail.com, lebedev.ri@gmail.com, llvm-bugs@lists.llvm.org, llvm-dev@redking.me.uk, nikita.ppv@gmail.com, spatel+llvm@rotateright.com
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<pre>AVX512 has the VPTERNLOG instructions which can be used to describe all truth
table lookups for a 3bit index created from the same bit from 3 registers and a
i8 immediate control word.
It'd be very useful to use this to combine ternary logic patterns using this
DAG node and lower to optimized bitops patterns on all SSE/AVX targets, not
just AVX512.
This is a big generalization of the canonicalizeBitSelect function that we
already have.
Examples can be found at:
<a href="http://www.0x80.pl/articles/avx512-ternary-functions.html">http://www.0x80.pl/articles/avx512-ternary-functions.html</a>
<a href="https://github.com/WojciechMula/ternary-logic">https://github.com/WojciechMula/ternary-logic</a></pre>
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