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<base href="https://bugs.llvm.org/">
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<body><table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - loop-extract-single: Instruction does not dominate all uses!"
href="https://bugs.llvm.org/show_bug.cgi?id=41285">41285</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>loop-extract-single: Instruction does not dominate all uses!
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
<tr>
<th>OS</th>
<td>Linux
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>enhancement
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Scalar Optimizations
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>cszide@163.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
</tr></table>
<p>
<div>
<pre>Created <span class=""><a href="attachment.cgi?id=21692" name="attach_21692" title="IR file of testcase">attachment 21692</a> <a href="attachment.cgi?id=21692&action=edit" title="IR file of testcase">[details]</a></span>
IR file of testcase
$clang -v
clang version 9.0.0 (trunk 355281)
Target: x86_64-unknown-linux-gnu
Thread model: posix
InstalledDir: /home/jack-zhou/Documents/llvm/llvm_truck/llvm/build4/bin
Found candidate GCC installation: /usr/lib/gcc/i686-linux-gnu/8
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/5
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/5.5.0
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/6
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/6.5.0
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/7
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/7.3.0
Found candidate GCC installation: /usr/lib/gcc/x86_64-linux-gnu/8
Selected GCC installation: /usr/lib/gcc/x86_64-linux-gnu/7.3.0
Candidate multilib: .;@m64
Candidate multilib: 32;@m32
Candidate multilib: x32;@mx32
Selected multilib: .;@m64
$opt -loop-extract-single bugpoint-reduced-simplified.ll
Instruction does not dominate all uses!
%0 = alloca [5 x i8], align 1
%.0.sroa_idx.us = getelementptr inbounds [5 x i8], [5 x i8]* %0, i64 0, i64 0
in function d
LLVM ERROR: Broken function found, compilation aborted!
----------------------------------------------------------
define dso_local void @d() #0 {
%1 = alloca [5 x i8], align 1
%.0.sroa_idx = getelementptr inbounds [5 x i8], [5 x i8]* %1, i64 0, i64 0
%.0.sroa_idx.us = getelementptr inbounds [5 x i8], [5 x i8]* %1, i64 0, i64 0
br label %2
; <label>:2: ; preds = %Flow21, %0
br i1 false, label %.split.us, label %..split_crit_edge
..split_crit_edge: ; preds = %2
br label %.split
.split.us: ; preds = %2
br i1 undef, label %.split.us.split.us, label
%.split.us..split.us.split_crit_edge
.split.us..split.us.split_crit_edge: ; preds = %.split.us
br label %.split.us.split
.split.us.split.us: ; preds = %.split.us
br label %3
; <label>:3: ; preds = %Flow17.us.us,
%.split.us.split.us
br i1 true, label %4, label %Flow17.us.us
; <label>:4: ; preds = %3
br i1 true, label %5, label %Flow.us.us
; <label>:5: ; preds = %4
br label %Flow.us.us
Flow.us.us: ; preds = %5, %4
br i1 undef, label %6, label %7
; <label>:6: ; preds = %Flow.us.us
br label %7
; <label>:7: ; preds = %6, %Flow.us.us
br label %LeafBlock.us.us
LeafBlock.us.us: ; preds = %7
br i1 undef, label %8, label %Flow18.us.us
; <label>:8: ; preds = %LeafBlock.us.us
br label %Flow18.us.us
Flow18.us.us: ; preds = %8,
%LeafBlock.us.us
br label %Flow17.us.us
Flow17.us.us: ; preds = %Flow18.us.us, %3
br i1 undef, label %Flow19.us-lcssa.us.us-lcssa.us, label %3
Flow19.us-lcssa.us.us-lcssa.us: ; preds = %Flow17.us.us
br label %Flow19.us-lcssa.us
.split.us.split: ; preds =
%.split.us..split.us.split_crit_edge
br label %9
; <label>:9: ; preds = %Flow17.us,
%.split.us.split
br i1 true, label %10, label %Flow17.us
; <label>:10: ; preds = %9
call void @llvm.lifetime.start.p0i8(i64 5, i8* %.0.sroa_idx.us)
br i1 false, label %11, label %Flow.us
; <label>:11: ; preds = %10
br label %Flow.us
Flow.us: ; preds = %11, %10
br i1 undef, label %12, label %13
; <label>:12: ; preds = %Flow.us
br label %13
; <label>:13: ; preds = %12, %Flow.us
call void @llvm.lifetime.end.p0i8(i64 5, i8* %.0.sroa_idx.us)
br label %LeafBlock.us
LeafBlock.us: ; preds = %13
br i1 undef, label %14, label %Flow18.us
; <label>:14: ; preds = %LeafBlock.us
br label %Flow18.us
Flow18.us: ; preds = %14, %LeafBlock.us
br label %Flow17.us
Flow17.us: ; preds = %Flow18.us, %9
br i1 false, label %Flow19.us-lcssa.us.us-lcssa, label %9
Flow19.us-lcssa.us.us-lcssa: ; preds = %Flow17.us
br label %Flow19.us-lcssa.us
Flow19.us-lcssa.us: ; preds =
%Flow19.us-lcssa.us.us-lcssa, %Flow19.us-lcssa.us.us-lcssa.us
br label %Flow19
.split: ; preds = %..split_crit_edge
br label %15
; <label>:15: ; preds = %Flow17, %.split
br i1 false, label %16, label %Flow17
; <label>:16: ; preds = %15
call void @llvm.lifetime.start.p0i8(i64 5, i8* %.0.sroa_idx)
br i1 undef, label %18, label %Flow
Flow: ; preds = %18, %16
br i1 undef, label %17, label %19
; <label>:17: ; preds = %Flow
br label %19
; <label>:18: ; preds = %16
br label %Flow
Flow17: ; preds = %Flow18, %15
br i1 undef, label %Flow19.us-lcssa, label %15
; <label>:19: ; preds = %17, %Flow
call void @llvm.lifetime.end.p0i8(i64 5, i8* %.0.sroa_idx)
br label %LeafBlock
LeafBlock: ; preds = %19
br i1 undef, label %20, label %Flow18
; <label>:20: ; preds = %LeafBlock
br label %Flow18
Flow18: ; preds = %20, %LeafBlock
br label %Flow17
Flow19.us-lcssa: ; preds = %Flow17
br label %Flow19
Flow19: ; preds = %Flow19.us-lcssa,
%Flow19.us-lcssa.us
br i1 undef, label %21, label %Flow20
; <label>:21: ; preds = %Flow19
br label %Flow20
Flow20: ; preds = %21, %Flow19
br i1 undef, label %NewDefault, label %22
NewDefault: ; preds = %Flow20
br label %22
; <label>:22: ; preds = %NewDefault,
%Flow20
br label %LeafBlock15
LeafBlock15: ; preds = %22
br i1 undef, label %23, label %Flow21
; <label>:23: ; preds = %LeafBlock15
br label %24
Flow21: ; preds = %24, %LeafBlock15
br i1 undef, label %NewDefault14, label %2
; <label>:24: ; preds = %23
br label %Flow21
NewDefault14: ; preds = %Flow21
br label %25
; <label>:25: ; preds = %NewDefault14
br label %26
; <label>:26: ; preds = %25
ret void
}</pre>
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