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<base href="https://bugs.llvm.org/">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - Some NEON load instructions don't use preferred vector type alignment"
href="https://bugs.llvm.org/show_bug.cgi?id=41245">41245</a>
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<th>Summary</th>
<td>Some NEON load instructions don't use preferred vector type alignment
</td>
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>8.0
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>MacOS X
</td>
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<th>Status</th>
<td>NEW
</td>
</tr>
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<th>Severity</th>
<td>enhancement
</td>
</tr>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>Backend: ARM
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
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<th>Reporter</th>
<td>andrey.vihrov@gmail.com
</td>
</tr>
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org, peter.smith@linaro.org, Ties.Stuij@arm.com
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<pre>Created <span class=""><a href="attachment.cgi?id=21676" name="attach_21676" title="Sample IR code">attachment 21676</a> <a href="attachment.cgi?id=21676&action=edit" title="Sample IR code">[details]</a></span>
Sample IR code
Consider the following IR code:
define i32 @bar(<4 x i32>*) {
%2 = load <4 x i32>, <4 x i32>* %0
%3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 1, i32
undef, i32 undef, i32 undef>
%4 = extractelement <4 x i32> %3, i32 0
ret i32 %4
}
When compiled to 32-bit ARM assembly code, this generates
_bar:
vld2.32 {d16, d17, d18, d19}, [r0:256]
vmov.32 r0, d18[0]
bx lr
According to <a href="https://llvm.org/doxygen/DataLayout_8cpp_source.html#l00534">https://llvm.org/doxygen/DataLayout_8cpp_source.html#l00534</a>
(DataLayout::getAlignmentInfo()), the preferred alignment for a vector of 4
32-bit integers should be 16 bytes, whereas here the vector is accessed with 32
byte alignment.
The problem disappears if explicit alignment is added to the load IR
instruction or if the shufflevector IR instruction is removed.
A more detailed sample and output assembly are attached. We can see that:
* The alloca in foo resulted into a 16 byte = 128 bit aligned stack allocation
(ok);
* The constant vector (from foo) has got a 16 byte aligned storage (ok);
* The vld1.64 instruction (that loads the constant vector) assumes 16 byte
alignment (ok);
* The vst1.64 instruction in foo (store to the alloca) assumes 16 byte
alignment as well (ok);
* The vld2.32 instruction in bar (combined load + shufflevector IR
instructions) assumes 32 byte alignment (bug?)
The problem gets "fixed" by running InstCombine optimization pass on the IR
before compilation. The optimization pass however just adds an explicit
alignment to the load instruction equal to the preferred alignment for <4 x
i32>.</pre>
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