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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [X86] FastSHLD optimization doesn't work well with TwoAddressInstruction pass"
href="https://bugs.llvm.org/show_bug.cgi?id=41055">41055</a>
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<th>Summary</th>
<td>[X86] FastSHLD optimization doesn't work well with TwoAddressInstruction pass
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<th>Product</th>
<td>libraries
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Windows NT
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>enhancement
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: X86
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>craig.topper@gmail.com
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<th>CC</th>
<td>craig.topper@gmail.com, llvm-bugs@lists.llvm.org, llvm-dev@redking.me.uk, spatel+llvm@rotateright.com
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<div>
<pre>We have a special case to use a SHLD for rotate by immediate on Sandybridge and
Ivybridge. This avoids a dependecy on previous flag writers due to the strange
behavior of the flags for rotate. The hardware on these CPUs has special
support for this idiom, but it requires that the 2 registers used by the SHLD
are the same physical register.
Unfortunately, the TwoAddressInstruction pass has to insert a COPY in front of
the SHLD to leave SSA form. This COPY will then become the input to the tied
src/dest pair. it will not be used for the other source. If the coalescer
doesn't remove this copy and the register allocator chooses a different
register for the input and output of the copy, then we will not have the same
physical registers for the SHLD instruction. So the hardware optimization won't
trigger.
The easiest way I can see to overcome this is to create a pseudo instruction in
X86 that will make the TwoAddressInstruction only see a single source. We can
expand it after register allocation to SHLD with the same source used twice.</pre>
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