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    <head>
      <base href="https://bugs.llvm.org/">
    </head>
    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_CONFIRMED "
   title="CONFIRMED - ISel crashes on SIMD setcc / setlt"
   href="https://bugs.llvm.org/show_bug.cgi?id=40912">40912</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>ISel crashes on SIMD setcc / setlt
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>libraries
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>Linux
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>CONFIRMED
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>enhancement
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Backend: WebAssembly
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>tlively@google.com
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>tlively@google.com
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>llvm-bugs@lists.llvm.org, srj@google.com
          </td>
        </tr></table>
      <p>
        <div>
        <pre>Reported error was

LLVM ERROR: Cannot select: t65: v4i32 = setcc t13, t17, setlt:ch
  t13: v4f32 = fmul nnan ninf nsz contract afn reassoc t11, t11
    t11: v4f32,ch = load<(load 16 from %ir.lsr.iv190192, !tbaa !32)> t0, t2,
undef:i32
      t2: i32,ch = CopyFromReg t0, Register:i32 %107
        t1: i32 = Register %107
      t10: i32 = undef
    t11: v4f32,ch = load<(load 16 from %ir.lsr.iv190192, !tbaa !32)> t0, t2,
undef:i32
      t2: i32,ch = CopyFromReg t0, Register:i32 %107
        t1: i32 = Register %107
      t10: i32 = undef
  t17: v4f32 = fsub nnan ninf nsz contract afn reassoc t16, t14
    t16: v4f32 = BUILD_VECTOR ConstantFP:f32<4.000000e+00>,
ConstantFP:f32<4.000000e+00>, ConstantFP:f32<4.000000e+00>,
ConstantFP:f32<4.000000e+00>
      t15: f32 = ConstantFP<4.000000e+00>
      t15: f32 = ConstantFP<4.000000e+00>
      t15: f32 = ConstantFP<4.000000e+00>
      t15: f32 = ConstantFP<4.000000e+00>
    t14: v4f32 = fmul nnan ninf nsz contract afn reassoc t12, t12
      t12: v4f32,ch = load<(load 16 from %ir.lsr.iv184186, !tbaa !35)> t0, t4,
undef:i32
        t4: i32,ch = CopyFromReg t0, Register:i32 %108
          t3: i32 = Register %108
        t10: i32 = undef
      t12: v4f32,ch = load<(load 16 from %ir.lsr.iv184186, !tbaa !35)> t0, t4,
undef:i32
        t4: i32,ch = CopyFromReg t0, Register:i32 %108
          t3: i32 = Register %108
        t10: i32 = undef</pre>
        </div>
      </p>


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