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    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - Missing redundancy elimination for uadd.with.overflow and manual overflow check"
   href="https://bugs.llvm.org/show_bug.cgi?id=40846">40846</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>Missing redundancy elimination for uadd.with.overflow and manual overflow check
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>libraries
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>All
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>All
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>enhancement
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Scalar Optimizations
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>nikita.ppv@gmail.com
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>llvm-bugs@lists.llvm.org
          </td>
        </tr></table>
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        <div>
        <pre>Originally reported at: <a href="https://github.com/rust-lang/rust/issues/58692">https://github.com/rust-lang/rust/issues/58692</a>

The following IR remains unchanged under opt -O3:

define i1 @test(i64 %x, i64 %y) nounwind {
  %a = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %x, i64 %y)
  %b = extractvalue { i64, i1 } %a, 1
  br i1 %b, label %trap, label %bb

bb:
  %c = extractvalue { i64, i1 } %a, 0
  %d = icmp ult i64 %c, %x
  ret i1 %d

trap:
  call void @llvm.trap()
  unreachable
}

declare { i64, i1 } @llvm.uadd.with.overflow.i64(i64, i64)
declare void @llvm.trap()

Here %d is the same as %b, and must be false in %bb by implication.

I think this should be fairly easy to fix (at least for this specific case)
with an instcombine pattern that converts the icmp into an extract, and CSE/GVN
will take care of the rest.</pre>
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