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<base href="https://bugs.llvm.org/">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [Subregliveness] Bad machine code: Defining instruction does not modify register"
href="https://bugs.llvm.org/show_bug.cgi?id=40835">40835</a>
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<th>Summary</th>
<td>[Subregliveness] Bad machine code: Defining instruction does not modify register
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
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<th>OS</th>
<td>Linux
</td>
</tr>
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<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>enhancement
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Register Allocator
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>paulsson@linux.vnet.ibm.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org, quentin.colombet@gmail.com
</td>
</tr></table>
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<pre>Created <span class=""><a href="attachment.cgi?id=21509" name="attach_21509" title="reduced testcase">attachment 21509</a> <a href="attachment.cgi?id=21509&action=edit" title="reduced testcase">[details]</a></span>
reduced testcase
llc -mcpu=z13 -O3 tc_subregliv_defnotmod.ll -o out.s -systemz-subreg-liveness
-verify-machineinstrs
# After Simple Register Coalescing
********** INTERVALS **********
%0 [144r,384r:0) 0@144r L00000008 [144r,384r:0) 0@144r L00000001
[144r,384r:0) 0@144r weight:0.000000e+00
%1 [16r,32r:0) 0@16r weight:0.000000e+00
%2 [48r,64r:0) 0@48r weight:0.000000e+00
%4 [176r,192r:0)[192r,224r:1)[224r,240r:2) 0@176r 1@192r 2@224r L00000008
[176r,192r:0)[192r,224r:1)[224r,240r:2) 0@176r 1@192r 2@224r L00000001
[176r,176d:0)[192r,192d:1) 0@176r 1@192r weight:0.000000e+00
%6 [240r,256r:0) 0@240r weight:0.000000e+00
%7 [256r,272r:0) 0@256r weight:0.000000e+00
%10 [288r,304r:0)[304r,384r:1)[384r,432r:2) 0@288r 1@304r 2@384r L00000008
[288r,384r:0)[384r,432r:1) 0@288r 1@384r 2@x L00000001
[288r,384r:0)[384r,384d:1) 0@288r 1@384r 2@x L00000006
[304r,384r:0)[384r,384d:1) 0@304r 1@384r weight:0.000000e+00
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function main: NoPHIs, TracksLiveness
0B bb.0 (%ir-block.0):
successors: %bb.2(0x7fffffff), %bb.1(0x00000001); %bb.2(100.00%),
%bb.1(0.00%)
16B %1:addr64bit = LARL @g_48
32B MVI %1:addr64bit, 0, 43 :: (store 1 into @g_48, align 2, !tbaa !1)
48B %2:grx32bit = LHIMux 0
64B CHIMux %2:grx32bit, 0, implicit-def $cc
80B BRC 14, 6, %bb.2, implicit killed $cc
96B J %bb.1
112B bb.1 (%ir-block.3):
; predecessors: %bb.0
128B bb.2 (%ir-block.4):
; predecessors: %bb.0
successors: %bb.4(0x7fffffff), %bb.3(0x00000001); %bb.4(100.00%),
%bb.3(0.00%)
144B %0:gr64bit = LGHI 43
176B %4:gr64bit = LGHI 43
192B %4.subreg_l32:gr64bit = MSR %4.subreg_l32:gr64bit(tied-def 0),
%4.subreg_l32:gr64bit
224B %4.subreg_l32:gr64bit = AHIMux %4.subreg_l32:gr64bit(tied-def 0), 9,
implicit-def dead $cc
240B %6:gr32bit = LLCRMux %4.subreg_l32:gr64bit
256B %7:gr32bit = nsw LCR %6:gr32bit, implicit-def dead $cc
272B STRL %7:gr32bit, @g_80 :: (store 4 into @g_80, !tbaa !4)
288B undef %10.subreg_l64:gr128bit = LGFI -245143785
304B %10.subreg_h64:gr128bit = LLILL 0
384B %10:gr128bit = DLGR %10:gr128bit(tied-def 0), %0:gr64bit
432B CHIMux %10.subreg_l32:gr128bit, 0, implicit-def $cc
448B BRC 14, 8, %bb.4, implicit killed $cc
464B J %bb.3
480B bb.3 (%ir-block.16):
; predecessors: %bb.2
496B bb.4 (%ir-block.17):
; predecessors: %bb.2
512B Return
# End machine code for function main.
*** Bad machine code: Defining instruction does not modify register ***
- function: main
- basic block: %bb.2 (0x583dda8) [128B;480B)
- instruction: 192B %4.subreg_l32:gr64bit = MSR
%4.subreg_l32:gr64bit(tied-def 0), %4.subreg_l32:gr64bit
- liverange: [176r,176d:0)[192r,192d:1) 0@176r 1@192r
- v. register: %4
- lanemask: 00000001
- ValNo: 1 (def 192r)
LLVM ERROR: Found 1 machine code errors.</pre>
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