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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [RISCV] [RV64] SelectionDAG loop due to ANY_EXTEND turned into SIGN_EXTEND and back again to ANY_EXTEND"
href="https://bugs.llvm.org/show_bug.cgi?id=40333">40333</a>
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<th>Summary</th>
<td>[RISCV] [RV64] SelectionDAG loop due to ANY_EXTEND turned into SIGN_EXTEND and back again to ANY_EXTEND
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
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<th>OS</th>
<td>Linux
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>enhancement
</td>
</tr>
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<th>Priority</th>
<td>P
</td>
</tr>
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<th>Component</th>
<td>Backend: RISC-V
</td>
</tr>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>rofirrim@gmail.com
</td>
</tr>
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
</tr></table>
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<div>
<pre>Created <span class=""><a href="attachment.cgi?id=21337" name="attach_21337" title="Reduced reproducer">attachment 21337</a> <a href="attachment.cgi?id=21337&action=edit" title="Reduced reproducer">[details]</a></span>
Reduced reproducer
Hi all,
there is a target-specific combiner in RISCVISelLowering.cpp to convert x =
ANY_EXTEND into x = SIGN_EXTEND. Once this happens, there is AND that uses 'x'
in "AND x, Constant:i64<255>" and then TargetLowering::SimplifyDemandedBits
determines that we don't need a SIGN_EXTEND in this case and changes it back to
ANY_EXTEND causing the loop.
Combining: t12: i64 = zero_extend t11
Creating new node: t25: i64 = any_extend t10
Creating constant: t26: i64 = Constant<255>
Creating new node: t27: i64 = and t25, Constant:i64<255>
... into: t27: i64 = and t25, Constant:i64<255>
[...]
Combining: t25: i64 = any_extend t10 \ Target combiner
Creating new node: t28: i64 = sign_extend t10 |
|
Replacing.1 t25: i64 = any_extend t10 |
|
With: t28: i64 = sign_extend t10 |
and 0 other values /
Combining: t27: i64 = and t28, Constant:i64<255> \ TLO::SimplifyDemandedBits
Creating new node: t29: i64 = any_extend t10 |
|
Replacing.2 t28: i64 = sign_extend t10 |
|
With: t29: i64 = any_extend t10 /
The attached testcase is a bugpoint-minimized input from an input in the
llvm-test-suite.
$ llc -mtriple=riscv64 bugpoint-reduced-simplified.ll -o - -debug
Kind regards,
Roger</pre>
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