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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - Incorrect liveness information after updating MBB live-ins through RDF"
href="https://bugs.llvm.org/show_bug.cgi?id=39960">39960</a>
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<th>Summary</th>
<td>Incorrect liveness information after updating MBB live-ins through RDF
</td>
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>All
</td>
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
</td>
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<th>Keywords</th>
<td>crash-on-invalid
</td>
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<th>Severity</th>
<td>enhancement
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: Hexagon
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>alexey.zhikhar@gmail.com
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<th>CC</th>
<td>kparzysz@codeaurora.org, llvm-bugs@lists.llvm.org
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<p>
<div>
<pre>Consider a case of an imaginary register R1 that is declared live-in in BB#1:
BB#0:
%R1 = define
...
BB#1:
Live Ins: %R1
… = use %R1
Then, the code went through an RDF-based transformation, which lead to updating
live-ins of each basic block:
BB#0:
%R1 = define
...
BB#1:
Live Ins: %R0
… = use %R1
But why do we have %R0 instead of %R1? One thing I didn't mention about this
imaginary processor is that R0 and R1 completely overlap with each other.
Nevertheless, the live-in information at this point is incorrect, which is
discovered by the machine instruction verifier.
My understanding of the reason behind this is that the data structure used by
rdf::Liveness:computeLiveIns() has a shortcoming: RegisterAggr stores register
units rather than registers, so loosing information is inevitable. Since R0 and
R1 share the same register unit, RDF picks the first register that corresponds
to the stored register unit.
Unfortunately, I cannot share the test case since it is written for our
out-of-tree backend; however, the bug should be relevant for each backend that
makes use of RDF.</pre>
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</p>
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