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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [llvm-mca] Investigate how to improve the load/store queue usage simulation in LSUnit."
href="https://bugs.llvm.org/show_bug.cgi?id=39830">39830</a>
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<th>Summary</th>
<td>[llvm-mca] Investigate how to improve the load/store queue usage simulation in LSUnit.
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<th>Product</th>
<td>tools
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
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<th>OS</th>
<td>Windows NT
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>enhancement
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>llvm-mca
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>andrea.dibiagio@gmail.com
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<th>CC</th>
<td>andrea.dibiagio@gmail.com, llvm-bugs@lists.llvm.org, matthew.davis@sony.com
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<p>
<div>
<pre>On some processors, load/store operations are split into multiple uOps. For
example, X86 AMD Jaguar natively supports 128-bit data types, but not 256-bit
data types. So, a 256-bit load is effectively split into two 128-bit loads, and
each split load consumes one 'LoadQueue' entry. For simplicity, this class
optimistically assumes that a load instruction only consumes one entry in the
LoadQueue. Similarly, store instructions only consume a single entry in the
StoreQueue.
In future, we should reassess the quality of this design, and consider
alternative approaches that let instructions specify the number of load/store
queue entries which they consume at dispatch stage.</pre>
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