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      <base href="https://bugs.llvm.org/">
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    <body><span class="vcard"><a class="email" href="mailto:spatel+llvm@rotateright.com" title="Sanjay Patel <spatel+llvm@rotateright.com>"> <span class="fn">Sanjay Patel</span></a>
</span> changed
          <a class="bz_bug_link 
          bz_status_RESOLVED  bz_closed"
   title="RESOLVED FIXED - hoist/sink vector cast ops to avoid illegal types?"
   href="https://bugs.llvm.org/show_bug.cgi?id=28160">bug 28160</a>
          <br>
             <table border="1" cellspacing="0" cellpadding="8">
          <tr>
            <th>What</th>
            <th>Removed</th>
            <th>Added</th>
          </tr>

         <tr>
           <td style="text-align:right;">Fixed By Commit(s)</td>
           <td>
                
           </td>
           <td>r301781
           </td>
         </tr>

         <tr>
           <td style="text-align:right;">Resolution</td>
           <td>---
           </td>
           <td>FIXED
           </td>
         </tr>

         <tr>
           <td style="text-align:right;">Status</td>
           <td>NEW
           </td>
           <td>RESOLVED
           </td>
         </tr></table>
      <p>
        <div>
            <b><a class="bz_bug_link 
          bz_status_RESOLVED  bz_closed"
   title="RESOLVED FIXED - hoist/sink vector cast ops to avoid illegal types?"
   href="https://bugs.llvm.org/show_bug.cgi?id=28160#c7">Comment # 7</a>
              on <a class="bz_bug_link 
          bz_status_RESOLVED  bz_closed"
   title="RESOLVED FIXED - hoist/sink vector cast ops to avoid illegal types?"
   href="https://bugs.llvm.org/show_bug.cgi?id=28160">bug 28160</a>
              from <span class="vcard"><a class="email" href="mailto:spatel+llvm@rotateright.com" title="Sanjay Patel <spatel+llvm@rotateright.com>"> <span class="fn">Sanjay Patel</span></a>
</span></b>
        <pre>We try to match vector select operand sizes with vector compares operand sizes
with:
<a href="https://reviews.llvm.org/rL301781">https://reviews.llvm.org/rL301781</a>

There were several other improvements in shuffle combining/lowering that also
helped.

That means we have better codegen in all cases on x86 independent of what we do
in IR for this kind of pattern:

$   ./llc -o - 28160opt.ll 
        cmpltps %xmm1, %xmm0
        shufps  $136, %xmm5, %xmm4      ## xmm4 = xmm4[0,2],xmm5[0,2]
        shufps  $136, %xmm3, %xmm2      ## xmm2 = xmm2[0,2],xmm3[0,2]
        andps   %xmm0, %xmm2
        andnps  %xmm4, %xmm0
        orps    %xmm2, %xmm0
        retq

$   ./llc -o - 28160opt.ll -mattr=avx
        vcmpltps        %xmm1, %xmm0, %xmm0
        vextractf128    $1, %ymm2, %xmm1
        vshufps $136, %xmm1, %xmm2, %xmm1 ## xmm1 = xmm2[0,2],xmm1[0,2]
        vextractf128    $1, %ymm3, %xmm2
        vshufps $136, %xmm2, %xmm3, %xmm2 ## xmm2 = xmm3[0,2],xmm2[0,2]
        vblendvps       %xmm0, %xmm1, %xmm2, %xmm0
        vzeroupper
        retq

$   ./llc -o - 28160opt.ll -mattr=avx2
        vcmpltps        %xmm1, %xmm0, %xmm0
        vpermilps       $232, %ymm2, %ymm1 ## ymm1 = ymm2[0,2,2,3,4,6,6,7]
        vpermpd $232, %ymm1, %ymm1      ## ymm1 = ymm1[0,2,2,3]
        vpermilps       $232, %ymm3, %ymm2 ## ymm2 = ymm3[0,2,2,3,4,6,6,7]
        vpermpd $232, %ymm2, %ymm2      ## ymm2 = ymm2[0,2,2,3]
        vblendvps       %xmm0, %xmm1, %xmm2, %xmm0
        vzeroupper
        retq

Test coverage looks good already for these transforms, so I don't think we need
to add anything specifically for this bug report.</pre>
        </div>
      </p>


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