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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - "ran out of registers during register allocation" with MEMCPY on Thumb1"
href="https://bugs.llvm.org/show_bug.cgi?id=39462">39462</a>
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<th>Summary</th>
<td>"ran out of registers during register allocation" with MEMCPY on Thumb1
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>All
</td>
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>enhancement
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: ARM
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>efriedma@codeaurora.org
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org, matze@braunis.de, peter.smith@linaro.org, peter@pcc.me.uk, Ties.Stuij@arm.com
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<pre>Testcase follows; run with "llc -enable-misched". Has something to do with the
MEMCPY pseudo (there are 8 total Thumb1 registers, and MEMCPY requires six; if
the register allocator messes up, it's easy to run out of registers). But I'm
not really familiar with the relevant code.
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv6m-none-unknown-musleabi"
@g = external constant [8 x i32], align 4
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly,
i8* nocapture readonly, i32, i1)
declare void @f1(i8* readonly, i32)
declare i8* @f2(i8*)
define i8* @f(i8* readonly %data, i32 %l, i8* %i, i8* %foo) {
entry:
call void @llvm.memcpy.p0i8.p0i8.i32(
i8* nonnull align 8 %foo,
i8* align 4 bitcast ([8 x i32]* @g to i8*),
i32 32, i1 false)
call void @f1(i8* %data, i32 %l)
%call = call i8* @f2(i8* %i)
ret i8* %call
}</pre>
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