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<base href="https://bugs.llvm.org/">
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<body><table border="1" cellspacing="0" cellpadding="8">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - Regression(r342175): ran out of registers during register allocation"
href="https://bugs.llvm.org/show_bug.cgi?id=39391">39391</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>Regression(r342175): ran out of registers during register allocation
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
<tr>
<th>OS</th>
<td>Linux
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>enhancement
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Backend: X86
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>peter@pcc.me.uk
</td>
</tr>
<tr>
<th>CC</th>
<td>craig.topper@gmail.com, llvm-bugs@lists.llvm.org
</td>
</tr></table>
<p>
<div>
<pre>source_filename = "reflection2.ll"
target triple = "i686-unknown-linux-gnu"
@f = global i8* zeroinitializer
define void @g() #0 {
entry:
%0 = load i8*, i8** @f
%1 = load atomic i8, i8* %0 monotonic, align 1
%d.h.h.h.h.h = bitcast i8* %0 to i64*
%2 = load atomic i64, i64* %d.h.h.h.h.h monotonic, align 8
%j.h = icmp eq i8 %1, 0
br i1 %j.h, label %k.end, label %.
.: ; preds = %., %entry
%3 = call i32 @m()
unreachable
k.end: ; preds = %entry
unreachable
}
declare i32 @m()
attributes #0 = { "no-frame-pointer-elim-non-leaf" }
$ llc reflection3.ll
LLVM ERROR: ran out of registers during register allocation
This regressed with r342175, although that change isn't directly to blame. That
change added a number of new register classes which changed heuristics used by
the machine scheduler, causing it to create an unsolvable problem for the
register allocator:
16B %0:gr32 = MOV32rm $noreg, 1, $noreg, @f, $noreg :: (dereferenceable
load 4 from @f)
64B $eax = MOV32r0 implicit-def dead $eflags
80B $edx = MOV32r0 implicit-def dead $eflags
96B $ecx = MOV32r0 implicit-def dead $eflags
112B $ebx = MOV32r0 implicit-def dead $eflags
120B %1:gr8 = MOV8rm %0:gr32, 1, $noreg, 0, $noreg :: (volatile load
monotonic 1 from %ir.0)
128B LCMPXCHG8B %0:gr32, 1, $noreg, 0, $noreg, implicit-def dead $eax,
implicit-def dead $edx, implicit-def dead $eflags, implicit killed $eax,
implicit
killed $ebx, implicit killed $ecx, implicit killed $edx :: (volatile load store
monotonic monotonic 8 on %ir.d.h.h.h.h.h, align 4)
144B TEST8rr %1:gr8, %1:gr8, implicit-def $eflags
160B JE_1 %bb.2, implicit killed $eflags
176B JMP_1 %bb.1
Since all possible MOV8rm destination registers are live at line 120B, a
destination register cannot be chosen.
The moves into physical registers started out as copies (which we know to keep
together with the user -- see biasPhysRegCopy), but the Simple Register
Coalescing pass replaced them with moves.</pre>
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