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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - GlobalISel: Investigate an efficient way to ensure load/store orderings"
href="https://bugs.llvm.org/show_bug.cgi?id=38368">38368</a>
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<th>Summary</th>
<td>GlobalISel: Investigate an efficient way to ensure load/store orderings
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>GlobalISel
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>aemerson@apple.com
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<pre>Load/store ordering needs some thought, as we currently don’t have a way to
easily check at the MI level what the ordering requirements are on a set of
memory operations. SelectionDAG uses the chains to ensure that they’re
scheduled to respect the orderings. How to achieve the same thing remains an
open question for GlobalISel.</pre>
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