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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [X86] Improve pass FixupLEA, and enable it on btver2."
href="https://bugs.llvm.org/show_bug.cgi?id=38225">38225</a>
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<th>Summary</th>
<td>[X86] Improve pass FixupLEA, and enable it on btver2.
</td>
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<th>Product</th>
<td>new-bugs
</td>
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<th>Version</th>
<td>unspecified
</td>
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<th>Hardware</th>
<td>PC
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<th>OS</th>
<td>Windows NT
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>new bugs
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>andrea.dibiagio@gmail.com
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<p>
<div>
<pre>Three-operands LEA instructions are slow on btver2 too. So we should enable
FixupLEAPass for btver2.
On Btver2, a LEA with a `Scale` != 1 is always slow.
We should teach the FixupLEAPass how to process those slow instructions too.
In particular - using the same notation in FixupLEAPass - we should
`processInstructionsForBtver()`. Currently, we only
`processInstructionsForSLM()`.
The core logic in method `processInstrForSlow3OpLEA()` is good for btver2.
The only Intel specific portion of that code is related to the call to helper
function `hasInefficientLEABaseReg()`.
We should slightly restructure that logic, so that it makes sense for AMD
processors too.
The bottom line is:
we should try to slightly restructure the code in FixupLEAPass, so that the
pass can be enable on more subtargets. It would definitely help improving the
codegen for btver2. I think it would also be beneficial to other AMD processors
which may suffer for the same problematic LEA.</pre>
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