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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [AMDGPU][MC][GFX9] Invalid number of src operands for ds_[read/write]_addtid_b32"
href="https://bugs.llvm.org/show_bug.cgi?id=37941">37941</a>
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<th>Summary</th>
<td>[AMDGPU][MC][GFX9] Invalid number of src operands for ds_[read/write]_addtid_b32
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>enhancement
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: AMDGPU
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>dpreobrazhensky@luxoft.com
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<pre>LLVM AMDGPU assembler expects 1 src operand (an address) for these opcodes:
ds_read_addtid_b32 v7 v8 offset:65535
SP3 assembler assumes that these instructions have no src operands:
ds_read_addtid_b32 v7 offset:65535
AMD documentation states: "no part of the address comes from a VGPR".</pre>
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