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<base href="https://bugs.llvm.org/">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [InstCombine] Failure to combine select/shuffle of equivalent instructions with constants"
href="https://bugs.llvm.org/show_bug.cgi?id=37806">37806</a>
</td>
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<th>Summary</th>
<td>[InstCombine] Failure to combine select/shuffle of equivalent instructions with constants
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
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<th>OS</th>
<td>Windows NT
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>enhancement
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Scalar Optimizations
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>llvm-dev@redking.me.uk
</td>
</tr>
<tr>
<th>CC</th>
<td>a.bataev@hotmail.com, dtemirbulatov@gmail.com, llvm-bugs@lists.llvm.org, spatel+llvm@rotateright.com
</td>
</tr></table>
<p>
<div>
<pre>Below are examples of constant selects/shuffles of 2 instructions taking
constant inputs that could all be combined into a single instruction. There are
probably more equivalent instructions/patterns (+ floats type instructions as
well). Note these are all about removing shuffles/selects so hopefully the
issue of creating them in instcombine won't raise its head.
This is very similar to [<a class="bz_bug_link
bz_status_ASSIGNED "
title="ASSIGNED - Failure to vectorize mixture of integer multiplies and shift lefts"
href="show_bug.cgi?id=31572">Bug #31572</a>] which was concerned about missing
vectorizations of equivalent instructions. My hope is that after D48174 et al
have landed I can then extend the "alt opcode" system in SLP so that we can
accept most pairs of instructions (not just ADD+SUB or FADD+FSUB) - vectorize
them with a select (costs permitting) and then let instcombine merge them if it
can via this bug.
define <4 x i32> @shuffle_add_v4i32(<4 x i32> %v0, <4 x i32> %v1) {
%1 = add <4 x i32> %v0, <i32 1, i32 2, i32 4, i32 4>
%2 = add <4 x i32> %v0, <i32 0, i32 0, i32 2, i32 2>
%3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 0, i32 5, i32
6, i32 7>
ret <4 x i32> %3
}
define <4 x i32> @select_sub_v4i32(<4 x i32> %v0, <4 x i32> %v1) {
%1 = sub <4 x i32> %v0, <i32 1, i32 2, i32 4, i32 4>
%2 = sub <4 x i32> %v0, <i32 0, i32 0, i32 2, i32 2>
%3 = select <4 x i1> <i1 -1, i1 0, i1 0, i1 -1>, <4 x i32> %1, <4 x i32> %2
ret <4 x i32> %3
}
define <4 x i32> @shuffle_add_sub_v4i32(<4 x i32> %v0, <4 x i32> %v1) {
%1 = add <4 x i32> %v0, <i32 1, i32 2, i32 4, i32 4>
%2 = sub <4 x i32> %v0, <i32 0, i32 0, i32 2, i32 2>
%3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 0, i32 5, i32
6, i32 7>
ret <4 x i32> %3
}
define <4 x i32> @shuffle_mul_v4i32(<4 x i32> %v0, <4 x i32> %v1) {
%1 = mul <4 x i32> %v0, <i32 1, i32 2, i32 4, i32 4>
%2 = mul <4 x i32> %v0, <i32 0, i32 0, i32 2, i32 2>
%3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 0, i32 5, i32
6, i32 7>
ret <4 x i32> %3
}
define <4 x i32> @shuffle_shl_v4i32(<4 x i32> %v0, <4 x i32> %v1) {
%1 = shl <4 x i32> %v0, <i32 0, i32 1, i32 2, i32 2>
%2 = shl <4 x i32> %v0, <i32 0, i32 0, i32 2, i32 2>
%3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 0, i32 5, i32
6, i32 7>
ret <4 x i32> %3
}
define <4 x i32> @shuffle_mul_shl_v4i32(<4 x i32> %v0, <4 x i32> %v1) {
%1 = mul <4 x i32> %v0, <i32 1, i32 2, i32 3, i32 4>
%2 = shl <4 x i32> %v0, <i32 0, i32 0, i32 2, i32 2>
%3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 0, i32 5, i32
6, i32 7>
ret <4 x i32> %3
}}</pre>
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