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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [X86] SLM has incorrect scheduling information for PMULLD"
href="https://bugs.llvm.org/show_bug.cgi?id=37059">37059</a>
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<th>Summary</th>
<td>[X86] SLM has incorrect scheduling information for PMULLD
</td>
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Windows NT
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<th>Status</th>
<td>NEW
</td>
</tr>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: X86
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>craig.topper@gmail.com
</td>
</tr>
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
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<p>
<div>
<pre>I had tried to fix this in r328914, but got perf regressions in some benchmarks
in Intel's internal list. So I reverted it back to old behavior in r329593.
Looking at the benchmarks, they regressed in 32-bit mode and it looks like
register pressure may have increased leading to additional spills. But I
thought 32-bit mode scheduling favored register pressure so I'm not sure what's
going on.</pre>
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</p>
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