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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [X86] SandyBridge/Haswell/Broadwell/Skylake scheduler models lose the ReadAdvance information for all instructions that load from memory and read another operand from a register"
href="https://bugs.llvm.org/show_bug.cgi?id=36951">36951</a>
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<th>Summary</th>
<td>[X86] SandyBridge/Haswell/Broadwell/Skylake scheduler models lose the ReadAdvance information for all instructions that load from memory and read another operand from a register
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<th>Product</th>
<td>libraries
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<th>Version</th>
<td>trunk
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<th>Hardware</th>
<td>PC
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<th>OS</th>
<td>Windows NT
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>enhancement
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: X86
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>craig.topper@gmail.com
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<p>
<div>
<pre>For example
[0,0] DeER . . addl %edi, %esi
[0,1] D=eeeeeeER addl (%rdi), %esi
The second instruction shouldn't have to wait on the first instruction to
writeback before it can execute.</pre>
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