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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [AMDGPU][MC] Unaligned SGPR pairs/quads/etc are disassembled as if they were aligned"
href="https://bugs.llvm.org/show_bug.cgi?id=36851">36851</a>
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<th>Summary</th>
<td>[AMDGPU][MC] Unaligned SGPR pairs/quads/etc are disassembled as if they were aligned
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<th>Product</th>
<td>libraries
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>enhancement
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: AMDGPU
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>dpreobrazhensky@luxoft.com
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<pre>This is a generic problem which affects both dst and src SGPR operands with
size greater than 32. These operands must be aligned to 2 or 4 so encoding an
odd register is incorrect and would trigger an exception if executed.
Our implementation defines only valid pairs of registers, e.g. s[0:1] but not
s[1:2] so correct disassembly is not possible. Currently disassembler issues a
warning and uses a nearest correctly aligned pair/quad of registers. (Due to
llvm disassembler quirk, the warning is not printed.)
Technically speaking, it is possible to define all incorrect register
pairs/quads etc but this looks like an overkill to me.
Personally I think current implementation is fine and needs no changes.
What is your opinion?</pre>
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