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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [X86][SSE] Split gpr/vector WriteMove, WriteLoad, WriteStore scheduler classes"
href="https://bugs.llvm.org/show_bug.cgi?id=36726">36726</a>
</td>
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<th>Summary</th>
<td>[X86][SSE] Split gpr/vector WriteMove, WriteLoad, WriteStore scheduler classes
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
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<th>Hardware</th>
<td>PC
</td>
</tr>
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<th>OS</th>
<td>Windows NT
</td>
</tr>
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<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>enhancement
</td>
</tr>
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<th>Priority</th>
<td>P
</td>
</tr>
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<th>Component</th>
<td>Backend: X86
</td>
</tr>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>llvm-dev@redking.me.uk
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
</tr>
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<th>Blocks</th>
<td>32325
</td>
</tr></table>
<p>
<div>
<pre>We currently use WriteMove, WriteLoad, WriteStore for x86 gpr, vector and mask
registers.
These need to be split to better account for differences in behaviour without
requiring full overloading of the scheduling of individual instructions.</pre>
</div>
</p>
<div id="referenced">
<hr style="border: 1px dashed #969696">
<b>Referenced Bugs:</b>
<ul>
<li>
[<a class="bz_bug_link
bz_status_NEW "
title="NEW - [META][X86] Improve implementation and use of X86 scheduler models"
href="https://bugs.llvm.org/show_bug.cgi?id=32325">Bug 32325</a>] [META][X86] Improve implementation and use of X86 scheduler models
</li>
</ul>
</div>
<br>
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