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<base href="https://bugs.llvm.org/">
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<body><table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - llvm.experimental.vector.reduce.{fadd,fmul} incorrect for non-unit accumulators"
href="https://bugs.llvm.org/show_bug.cgi?id=36734">36734</a>
</td>
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<tr>
<th>Summary</th>
<td>llvm.experimental.vector.reduce.{fadd,fmul} incorrect for non-unit accumulators
</td>
</tr>
<tr>
<th>Product</th>
<td>new-bugs
</td>
</tr>
<tr>
<th>Version</th>
<td>unspecified
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
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<th>OS</th>
<td>All
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>enhancement
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>new bugs
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>gonzalobg88@gmail.com
</td>
</tr>
<tr>
<th>CC</th>
<td>chandlerc@gmail.com, hfinkel@anl.gov, llvm-bugs@lists.llvm.org, llvm-dev@redking.me.uk
</td>
</tr></table>
<p>
<div>
<pre>This IR:
declare float @llvm.experimental.vector.reduce.fadd.f32.f32.v4f32(float, <4 x
float>)
declare float @llvm.experimental.vector.reduce.fmul.f32.f32.v4f32(float, <4 x
float>)
define internal float
@_ZN32simd_intrinsic_generic_reduction3foo17ha7e2b586cf5567bdE(<4 x float>*
noalias nocapture dereferenceable(16)) unnamed_addr #0 {
%2 = alloca float, align 4
%3 = load <4 x float>, <4 x float>* %0, align 16
%4 = call fast float
@llvm.experimental.vector.reduce.fadd.f32.f32.v4f32(float -1.000000e+00, <4 x
float> %3)
store float %4, float* %2, align 4
%5 = load float, float* %2, align 4
br label %6
; <label>:6: ; preds = %1
ret float %5
}
define internal float
@_ZN32simd_intrinsic_generic_reduction3bar17he2463f63ae652611E(<4 x float>*
noalias nocapture dereferenceable(16)) unnamed_addr #0 {
%2 = alloca float, align 4
%3 = load <4 x float>, <4 x float>* %0, align 16
%4 = call fast float
@llvm.experimental.vector.reduce.fmul.f32.f32.v4f32(float -1.000000e+00, <4 x
float> %3)
store float %4, float* %2, align 4
%5 = load float, float* %2, align 4
br label %6
; <label>:6: ; preds = %1
ret float %5
}
lowers to:
simd_intrinsic_generic_reduction::foo: # @simd_intrinsic_generic_reduction::foo
movaps xmm0, xmmword ptr [rdi]
movaps xmm1, xmm0
movhlps xmm1, xmm1 # xmm1 = xmm1[1,1]
addps xmm1, xmm0
movaps xmm0, xmm1
shufps xmm0, xmm0, 229 # xmm0 = xmm0[1,1,2,3]
addps xmm0, xmm1
movss dword ptr [rsp - 4], xmm0
ret
simd_intrinsic_generic_reduction::bar: # @simd_intrinsic_generic_reduction::bar
movaps xmm0, xmmword ptr [rdi]
movaps xmm1, xmm0
movhlps xmm1, xmm1 # xmm1 = xmm1[1,1]
mulps xmm1, xmm0
movaps xmm0, xmm1
shufps xmm0, xmm0, 229 # xmm0 = xmm0[1,1,2,3]
mulps xmm0, xmm1
movss dword ptr [rsp - 4], xmm0
ret
which is incorrect for any non unit accumulator (0. for fadd, and 1 for fmul).
For example, here -1 is the accumulator, and for the input (1, -2, 3, 4) this
should produce -1 + 1 - 2 + 3 + 4 = 5, but it produces 6 (it never adds the
accumulator to the result). Basically, these intrinsics only appear to work
correctly for an accumulator value of 0 for add, and 1 for mul...</pre>
</div>
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