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    <head>
      <base href="https://bugs.llvm.org/">
    </head>
    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - llvm.experimental.reduce.{and, any} don't lower properly for boolean vectors"
   href="https://bugs.llvm.org/show_bug.cgi?id=36702">36702</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>llvm.experimental.reduce.{and, any} don't lower properly for boolean vectors
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>new-bugs
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>unspecified
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>All
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>enhancement
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>new bugs
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>gonzalobg88@gmail.com
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>chandlerc@gmail.com, llvm-bugs@lists.llvm.org
          </td>
        </tr></table>
      <p>
        <div>
        <pre>I'd expect a way to be able to lower llvm.experimental.vector.reduce.and to
@llvm.x86.sse2.pmovmskb.128 on x86_64 and similar instructions in other
architectures when the input vectors are boolean vectors, that is, when their
lanes have either all bits cleared, or set. The same applies to
llvm.experimental.vector.reduce.any.

For example (thanks Chandler for coming up with this):

declare i1 @llvm.experimental.vector.reduce.and.i1.v16i1(<16 x i1>)
declare void @llvm.assume(i1)
declare void @a()
declare void @b()
define void @stdsimd_all_8x16(<16 x i8>* noalias nocapture dereferenceable(16)
%ptr) unnamed_addr #0 {
  %v = load <16 x i8>, <16 x i8>* %ptr, align 16
  %t = trunc <16 x i8> %v to <16 x i1>
  %e1 = sext <16 x i1> %t to <16 x i8>
  %e2 = icmp eq <16 x i8> %v, %e1
  %e3 = call i1 @llvm.experimental.vector.reduce.and.i1.v16i1(<16 x i1> %e2)
  call void @llvm.assume(i1 %e3)
  %x = call i1 @llvm.experimental.vector.reduce.and.i1.v16i1(<16 x i1> %t)
  br i1 %x, label %a, label %b
a:
  call void @a()
  ret void
b:
  call void @b()
  ret void
}

should emit:

 push    rbp
 mov     rbp, rsp
 movdqa  xmm0, xmmword, ptr, [rdi]
 pmovmskb eax, xmm0
 cmp     eax, 65535
 sete    al
 pop     rbp
 ret

and replacing "reduce.and" with "reduce.any" should emit:

 push    rbp
 mov     rbp, rsp
 movdqa  xmm0, xmmword, ptr, [rdi]
 pmovmskb eax, xmm0
 test    eax, eax
 setne   al
 pop     rbp
 ret</pre>
        </div>
      </p>


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