<html>
    <head>
      <base href="https://bugs.llvm.org/">
    </head>
    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - Bad machine code: Live segment doesn't end at a valid instruction"
   href="https://bugs.llvm.org/show_bug.cgi?id=36425">36425</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>Bad machine code: Live segment doesn't end at a valid instruction
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>libraries
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>Linux
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>enhancement
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Register Allocator
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>paulsson@linux.vnet.ibm.com
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>llvm-bugs@lists.llvm.org
          </td>
        </tr></table>
      <p>
        <div>
        <pre>Created <span class=""><a href="attachment.cgi?id=19890" name="attach_19890" title="reduced testcase">attachment 19890</a> <a href="attachment.cgi?id=19890&action=edit" title="reduced testcase">[details]</a></span>
reduced testcase

bin/llc -mtriple=s390x-linux-gnu -mcpu=z13 -O3 tc_liveseg.ll -o out.s
-disable-machine-dce -verify-machineinstrs

# After Simple Register Coalescing
********** INTERVALS **********
%0 [320r,320d:0)  0@320r weight:0.000000e+00
%1 [176r,224d:0)  0@176r weight:0.000000e+00
%3 [96r,176r:0)  0@96r weight:0.000000e+00
%12 [16r,32r:0)  0@16r weight:0.000000e+00
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function main: NoPHIs, TracksLiveness

0B      bb.0 (%ir-block.0):
          successors: %bb.1(0x40000000), %bb.2(0x40000000); %bb.1(50.00%),
%bb.2(50.00%)

16B       %12:grx32bit = LHIMux 0
32B       CHIMux %12, 0, implicit-def $cc
48B       BRC 14, 6, %bb.2, implicit killed $cc
64B       J %bb.1

80B     bb.1 (%ir-block.3):
        ; predecessors: %bb.0

96B       %3:gr64bit = LGRL @g_47; mem:LD8[bitcast (<{ i8, i8, i8, i8, i8, i8,
i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i64 }>* @g_47 to
i152*)](noalias=!2)(dereferenceable)
176B      %1:gr64bit = SRLG %3, $noreg, 8
320B      dead %0:gr64bit = LGHI 0

336B    bb.2 (%ir-block.5):
        ; predecessors: %bb.0


# End machine code for function main.

*** Bad machine code: Live segment doesn't end at a valid instruction ***
- function:    main
- basic block: %bb.1  (0x52de358) [80B;336B)
- liverange:   [176r,224d:0)  0@176r
- v. register: %1
- segment:     [176r,224d:0)
LLVM ERROR: Found 1 machine code errors.</pre>
        </div>
      </p>


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