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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [Hexagon] crash: CANNOT select: t16: v32i1 = HexagonISD::QFALSE"
href="https://bugs.llvm.org/show_bug.cgi?id=36320">36320</a>
</td>
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<tr>
<th>Summary</th>
<td>[Hexagon] crash: CANNOT select: t16: v32i1 = HexagonISD::QFALSE
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
<tr>
<th>OS</th>
<td>All
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>enhancement
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Backend: Hexagon
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>spatel+llvm@rotateright.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
</tr></table>
<p>
<div>
<pre>The following is a slight modification of an existing Hexagon regression test
at:
test/CodeGen/Hexagon/autohvx/isel-setcc-pair.ll
The only difference is that I have replaced an 'undef' operand of the vector
'and' instruction with a zero operand.
As noted in <a class="bz_bug_link
bz_status_NEW "
title="NEW - [DAGCombine] Difference in behaviour for SDIV undef, %X on scalar and vector types"
href="show_bug.cgi?id=36305">bug 36305</a>, our handling of undef operands in the DAG is wrong. In
this particular case, I think the difference is caused because currently in the
DAG for vectors we have:
and x, undef --> undef
But this is wrong. It should be:
and x, undef --> 0
-----------------------------------------------------------------------------
; RUN: llc -march=hexagon < %s | FileCheck %s
; Check that a setcc of a vector pair is handled (without crashing).
; CHECK: vcmp
target datalayout =
"e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon"
; Function Attrs: nounwind
define hidden fastcc void @fred(i32 %a0) #0 {
b1:
%v2 = insertelement <32 x i32> undef, i32 %a0, i32 0
%v3 = shufflevector <32 x i32> %v2, <32 x i32> undef, <32 x i32>
zeroinitializer
%v4 = icmp eq <32 x i32> %v3, undef
%v5 = and <32 x i1> zeroinitializer, %v4
br label %b6
b6: ; preds = %b1
%v7 = extractelement <32 x i1> %v5, i32 22
br i1 %v7, label %b8, label %b9
b8: ; preds = %b6
unreachable
b9: ; preds = %b6
unreachable
}
attributes #0 = { nounwind "target-cpu"="hexagonv60"
"target-features"="+hvx,+hvx-length64b" }</pre>
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