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<base href="https://bugs.llvm.org/">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [X86] Incorrect scheduler information for scalar multiplies in Znver1 scheduler model"
href="https://bugs.llvm.org/show_bug.cgi?id=36113">36113</a>
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<th>Summary</th>
<td>[X86] Incorrect scheduler information for scalar multiplies in Znver1 scheduler model
</td>
</tr>
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Windows NT
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: X86
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>craig.topper@gmail.com
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</tr>
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<p>
<div>
<pre>Due to funny naming of multiply instructions and weak regular expressions in
the scheduler model, the Znver1 scheduler model has incorrect information.
I've changed the regular expressions to explicit instruction lists to point out
the problem. I've left TODOs for the things that I added that are either wrong
or I'm not sure about.
Here is the current version of the file with the TODOs
def ZnWriteMul16 : SchedWriteRes<[ZnALU1, ZnMultiplier]> {
let Latency = 3;
}
def : InstRW<[ZnWriteMul16], (instrs IMUL16r, MUL16r)>;
def : InstRW<[ZnWriteMul16], (instrs IMUL16rr, IMUL16rri, IMUL16rri8)>; //
TODO: is this right?
def : InstRW<[ZnWriteMul16], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>; //
TODO: this is definitely wrong but matches what the instregex did.
// m16.
def ZnWriteMul16Ld : SchedWriteRes<[ZnAGU, ZnALU1, ZnMultiplier]> {
let Latency = 8;
}
def : InstRW<[ZnWriteMul16Ld, ReadAfterLd], (instrs IMUL16m, MUL16m)>;
// r32.
def ZnWriteMul32 : SchedWriteRes<[ZnALU1, ZnMultiplier]> {
let Latency = 3;
}
def : InstRW<[ZnWriteMul32], (instrs IMUL32r, MUL32r)>;
def : InstRW<[ZnWriteMul32], (instrs IMUL32rr, IMUL32rri, IMUL32rri8)>; //
TODO: is this right?
def : InstRW<[ZnWriteMul32], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8)>; //
TODO: this is definitely wrong but matches what the instregex did.
// m32.
def ZnWriteMul32Ld : SchedWriteRes<[ZnAGU, ZnALU1, ZnMultiplier]> {
let Latency = 8;
}
def : InstRW<[ZnWriteMul32Ld, ReadAfterLd], (instrs IMUL32m, MUL32m)>;
// r64.
def ZnWriteMul64 : SchedWriteRes<[ZnALU1, ZnMultiplier]> {
let Latency = 4;
let NumMicroOps = 2;
}
def : InstRW<[ZnWriteMul64], (instrs IMUL64r, MUL64r)>;
def : InstRW<[ZnWriteMul64], (instrs IMUL64rr, IMUL64rri8, IMUL64rri32)>; //
TODO: is this right?
def : InstRW<[ZnWriteMul64], (instrs IMUL64rm, IMUL64rmi32, IMUL64rmi8)>; //
TODO: this is definitely wrong but matches what the instregex did.</pre>
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