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    <head>
      <base href="https://bugs.llvm.org/">
    </head>
    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - [DAGCombine] Failure to recognise alternative ISD::ABS pattern"
   href="https://bugs.llvm.org/show_bug.cgi?id=36036">36036</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>[DAGCombine] Failure to recognise alternative ISD::ABS pattern
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>libraries
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>Windows NT
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>enhancement
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Common Code Generator Code
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>llvm-dev@redking.me.uk
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>llvm-bugs@lists.llvm.org, spatel+llvm@rotateright.com
          </td>
        </tr></table>
      <p>
        <div>
        <pre>__v4si abs(__v4si v) {
    __m128i sign = _mm_srai_epi32( v, 31 );
    return _mm_xor_si128( _mm_add_epi32( v, sign ), sign );
}
__v4si abs_alt(__v4si v) {
    __m128i sign = _mm_srai_epi32( v, 31 );
    return _mm_sub_epi32( _mm_xor_si128( v, sign ), sign );
}

define <4 x i32> @abs(<4 x i32>) {
  %2 = icmp slt <4 x i32> %0, zeroinitializer
  %3 = sub <4 x i32> zeroinitializer, %0
  %4 = select <4 x i1> %2, <4 x i32> %3, <4 x i32> %0
  ret <4 x i32> %4
}

define <4 x i32> @abs_alt(<4 x i32>) {
  %2 = ashr <4 x i32> %0, <i32 31, i32 31, i32 31, i32 31>
  %3 = xor <4 x i32> %2, %0
  %4 = sub <4 x i32> %3, %2
  ret <4 x i32> %4
}

llc -mcpu=btver2

abs:
  vpabsd %xmm0, %xmm0
  retq

abs_alt:
  vpsrad $31, %xmm0, %xmm1
  vpxor %xmm0, %xmm1, %xmm0
  vpsubd %xmm1, %xmm0, %xmm0
  retq</pre>
        </div>
      </p>


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