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      <base href="https://bugs.llvm.org/">
    </head>
    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - [meta][x86] Scheduler Driven Optimizations"
   href="https://bugs.llvm.org/show_bug.cgi?id=35784">35784</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>[meta][x86] Scheduler Driven Optimizations
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>libraries
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>Windows NT
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>enhancement
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Backend: X86
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>llvm-dev@redking.me.uk
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>andrea.dibiagio@gmail.com, andrew.v.tischenko@gmail.com, craig.topper@gmail.com, gadi.haber@intel.com, llvm-bugs@lists.llvm.org, spatel+llvm@rotateright.com, zvi.rackover@intel.com
          </td>
        </tr>

        <tr>
          <th>Blocks</th>
          <td>32325
          </td>
        </tr></table>
      <p>
        <div>
        <pre>Split off from <a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - Combining unary integer shuffles to PSHUFB"
   href="show_bug.cgi?id=26183">Bug #26183</a>.

With the scheduler models maturing we should be investigating ways to better
select between MC optimizations based on scheduler characteristics, register
pressure etc.

<a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - Combining unary integer shuffles to PSHUFB"
   href="show_bug.cgi?id=26183">Bug #26183</a> mentioned several X86 slow/fast features that could be replaced with
scheduler costings:

FeatureSlowBTMem
FeatureSlowSHLD
FeatureSlowUAMem16
FeatureSlowUAMem32
FeatureSlowDivide32
FeatureSlowDivide64

Some of these affect (older) CPUs that currently don't have a accurate
scheduler models - taking numbers from Agner is probably enough to be useful?

Additionally, the use of when to combine multiple shuffles to a single variable
shuffle mask keeps coming up. As well as the actual instruction cost, the cost
of loading the mask needs to be accurately modelled: register pressure? can it
be hoisted? etc.</pre>
        </div>
      </p>

        <div id="referenced">
          <hr style="border: 1px dashed #969696">
          <b>Referenced Bugs:</b>
          <ul>
              <li>
                [<a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - [META][X86] Improve implementation and use of X86 scheduler models"
   href="https://bugs.llvm.org/show_bug.cgi?id=32325">Bug 32325</a>] [META][X86] Improve implementation and use of X86 scheduler models
              </li>
          </ul>
        </div>
        <br>

      <hr>
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      <ul>
          <li>You are on the CC list for the bug.</li>
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