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    <head>
      <base href="https://bugs.llvm.org/">
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    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - [AMDGPU][MC] 256- and 512-bit tuples of ttmp registers should be supported"
   href="https://bugs.llvm.org/show_bug.cgi?id=35561">35561</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>[AMDGPU][MC] 256- and 512-bit tuples of ttmp registers should be supported
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>libraries
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>All
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>enhancement
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Backend: AMDGPU
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>dpreobrazhensky@luxoft.com
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>llvm-bugs@lists.llvm.org
          </td>
        </tr></table>
      <p>
        <div>
        <pre>Currently assembler supports only 64- and 128-bit ttmp tuples.

Examples of failing tests (gfx9):

s_load_dwordx8 ttmp[8:15], s[2:3], s0
s_buffer_load_dwordx16 ttmp[0:15], s[4:7], s0</pre>
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      </p>


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