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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - SREM/UREM can now be legal"
href="https://bugs.llvm.org/show_bug.cgi?id=35090">35090</a>
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<th>Summary</th>
<td>SREM/UREM can now be legal
</td>
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Linux
</td>
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: PowerPC
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>hfinkel@anl.gov
</td>
</tr>
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<th>CC</th>
<td>jtony@ca.ibm.com, llvm-bugs@lists.llvm.org, powerllvm@ca.ibm.com
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<p>
<div>
<pre>In lib/Target/PowerPC/PPCISelLowering.cpp, we have this:
// PowerPC has no SREM/UREM instructions unless we are on P9
// On P9 we may use a hardware instruction to compute the remainder.
// The instructions are not legalized directly because in the cases where the
// result of both the remainder and the division is required it is more
// efficient to compute the remainder from the result of the division rather
// than use the remainder instruction.
if (Subtarget.isISA3_0()) {
setOperationAction(ISD::SREM, MVT::i32, Custom);
setOperationAction(ISD::UREM, MVT::i32, Custom);
setOperationAction(ISD::SREM, MVT::i64, Custom);
setOperationAction(ISD::UREM, MVT::i64, Custom);
} else {
setOperationAction(ISD::SREM, MVT::i32, Expand);
setOperationAction(ISD::UREM, MVT::i32, Expand);
setOperationAction(ISD::SREM, MVT::i64, Expand);
setOperationAction(ISD::UREM, MVT::i64, Expand);
}
but as of:
[llvm] r312862 - [DivRempairs] add a pass to optimize div/rem pairs (PR31028)
the rationale for using custom lowering here should no longer be true. At the
IR level, we perform the transformation where the remainder is computed from
the result of the division when both a required. We should now be able to lower
these directly.</pre>
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