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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [X86] Masked EVEX instructions that produce less than 128-bits probably have incorrect patterns"
href="https://bugs.llvm.org/show_bug.cgi?id=34877">34877</a>
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<th>Summary</th>
<td>[X86] Masked EVEX instructions that produce less than 128-bits probably have incorrect patterns
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>enhancement
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: X86
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>craig.topper@gmail.com
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<p>
<div>
<pre>As far as I can tell from Intel's docs, instructions that write less than
128-bits like "vpmovwb xmm, xmm" or "vcvtpd2ps xmm, xmm" don't use the mask
register bits for the unwritten elements. Those elements are always zeroed
regardless of the mask. I think this means we can't match a regular vselect to
these instructions.</pre>
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