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<base href="https://bugs.llvm.org/">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - optimize for broadcast in 32-bit"
href="https://bugs.llvm.org/show_bug.cgi?id=34716">34716</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>optimize for broadcast in 32-bit
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
<tr>
<th>OS</th>
<td>Windows NT
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>enhancement
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Interprocedural Optimizations
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>Jina.nahias@intel.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
</tr></table>
<p>
<div>
<pre>for the following IR example:
define <8 x i64>@test(i32 %x0, i32 %x1){
%1= insertelement <2 x i32> undef, i32 %x0, i32 0
%2=insertelement <2 x i32> %1, i32 %x1, i32 1
%3=bitcast <2 x i32> %2 to i64
%vecinit.i.i = insertelement <8 x i64> undef, i64 %3, i32 0
%vecinit15.i.i = shufflevector <8 x i64> %vecinit.i.i, <8 x i64> undef, <8 x
i32> zeroinitializer
ret <8 x i64> %vecinit15.i.i
}
if we run in 32 bit (e.g: llc < %s -mtriple=i386-apple-darwin10 -mcpu=knl )it
gets translated to this assembly:
movl 4(%esp), %eax
movl 8(%esp), %ecx
vmovd %eax, %xmm0
vpinsrd $1, %ecx, %xmm0, %xmm0
vpinsrd $2, %eax, %xmm0, %xmm0
vpinsrd $3, %ecx, %xmm0, %xmm0
vinserti128 $1, %xmm0, %ymm0, %ymm0
vinserti64x4 $1, %ymm0, %zmm0, %zmm0
retl
we would like to get this assembly:
movl 4(%esp), %eax
movl 8(%esp), %ecx
vmovd %eax, %xmm0
vpinsrd $1, (%eax), %xmm0, %xmm0
vpbroadcastq %xmm0, %zmm0</pre>
</div>
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