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      <base href="https://bugs.llvm.org/">
    </head>
    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - [X86] Failure to prevent schedule across x87 control word instructions"
   href="https://bugs.llvm.org/show_bug.cgi?id=34454">34454</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>[X86] Failure to prevent schedule across x87 control word instructions
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>libraries
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>Windows NT
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>enhancement
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Backend: X86
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>llvm-dev@redking.me.uk
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>craig.topper@gmail.com, emaste@freebsd.org, gadi.haber@intel.com, llvm-bugs@lists.llvm.org, spatel+llvm@rotateright.com
          </td>
        </tr></table>
      <p>
        <div>
        <pre>Branched off from [<a class="bz_bug_link 
          bz_status_RESOLVED  bz_closed"
   title="RESOLVED FIXED - After r307529, sinl() test failures in FreeBSD's libm"
   href="show_bug.cgi?id=34080">Bug #34080</a>].

The partial SandyBridge schedule model (which is used for all default x86-64
targets) resulted in the scheduler moving some instructions across fldcw/fnstcw
instructions, affecting rounding of truncated stores etc.

The issue appears to be that we're incorrectly handling the control word
register dependency, which is odd because it looks like fldcw/fnstcw are
correctly flagged to cause side effects.

It could also be a chain issue in the fptosi store code in
X86TargetLowering::EmitInstrWithCustomInserter but I didn't notice anything.

Exposing this is tricky, and seems to involve applying rL307529 but not
rL310792.</pre>
        </div>
      </p>


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