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<base href="https://bugs.llvm.org/">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [MC][GFX9] Many VOP3 opcodes should support integer clamping"
href="https://bugs.llvm.org/show_bug.cgi?id=34152">34152</a>
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<th>Summary</th>
<td>[MC][GFX9] Many VOP3 opcodes should support integer clamping
</td>
</tr>
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<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>All
</td>
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<th>Status</th>
<td>NEW
</td>
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<tr>
<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>Backend: AMDGPU
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
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<th>Reporter</th>
<td>dpreobrazhensky@luxoft.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
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<p>
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<pre>Full list of affected opcodes:
v_lerp_u8
v_mqsad_pk_u16_u8
v_msad_u8
v_sad_hi_u8
v_sad_u16
v_sad_u8
v_ashrrev_i64
v_mad_i64_i32
v_mad_u64_u32
v_qsad_pk_u16_u8
v_mad_i16
v_mad_u16
v_bfe_i32
v_bfe_u32
v_mad_i32_i24
v_mad_u32_u24
v_max3_i32
v_max3_u32
v_med3_i32
v_med3_u32
v_min3_i32
v_min3_u32
v_mbcnt_hi_u32_b32
v_mbcnt_lo_u32_b32
v_mul_hi_i32
v_mul_hi_u32
v_mul_lo_u32
v_sad_u32
v_mqsad_u32_u8
v_sub_u32_e64
v_subrev_u32_e64
v_max_i16_e64
v_max_i32_e64
v_max_u16_e64
v_max_u32_e64
v_min_i16_e64
v_min_i32_e64
v_min_u16_e64
v_min_u32_e64
v_mul_hi_i32_i24_e64
v_mul_hi_u32_u24_e64
v_mul_i32_i24_e64
v_mul_lo_u16_e64
v_mul_u32_u24_e64
v_sub_u16_e64
v_subrev_u16_e64
v_add_u16_e64
v_ashrrev_i32_e64
v_bcnt_u32_b32
v_cvt_pk_i16_i32
v_cvt_pk_u16_u32
v_ffbh_i32_e64
v_ffbh_u32_e64
v_ashrrev_i16_e64
v_add_u32_e64
v_addc_u32_e64
v_subb_u32_e64
v_subbrev_u32_e64</pre>
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