<html>
    <head>
      <base href="https://bugs.llvm.org/">
    </head>
    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - ARMTargetLowering::isLegalAddressingMode can accept incorrect addressing modes for Thumb1 target"
   href="https://bugs.llvm.org/show_bug.cgi?id=34106">34106</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>ARMTargetLowering::isLegalAddressingMode can accept incorrect addressing modes for Thumb1 target
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>libraries
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>Linux
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>normal
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Backend: ARM
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>eastig@yandex.ru
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>llvm-bugs@lists.llvm.org
          </td>
        </tr></table>
      <p>
        <div>
        <pre>This bug report is a result of investigation of performance regressions on
Cortex-M0+ and Cortex-M23 triggered by the changes:
<a href="https://reviews.llvm.org/D34583">https://reviews.llvm.org/D34583</a>

See a discussion thread
<a href="http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20170731/475927.html">http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20170731/475927.html</a>
for more information about the investigation.

The current code of ARMTargetLowering::isLegalAddressingMode:

bool ARMTargetLowering::isLegalAddressingMode(const DataLayout &DL,
                                              const AddrMode &AM, Type *Ty,
                                              unsigned AS, Instruction *I)
const {
  EVT VT = getValueType(DL, Ty, true);
  if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
    return false;

  // Can never fold addr of global into load/store.
  if (AM.BaseGV)
    return false;

  switch (AM.Scale) {
  case 0:  // no scale reg, must be "r+i" or "r", or "i".
    break;
  case 1:
    if (Subtarget->isThumb1Only())
      return false;
    LLVM_FALLTHROUGH;
  default:
    // ARM doesn't support any R+R*scale+imm addr modes.
    if (AM.BaseOffs)
      return false;

    if (!VT.isSimple())
      return false;

    if (Subtarget->isThumb2())
      return isLegalT2ScaledAddressingMode(AM, VT);


For the Thumb1 target the code returns false when AM.Scale equals 1. It returns
true when AM.Scale equals 4, for example. AM.Scale == 1 which actually means no
scaling so the Thumb1 target can accept it. Other Scale values can be accepted
by the Thumb1 target because its addressing modes do not support scaling.</pre>
        </div>
      </p>


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