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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [mc][gfx9] V_MAD_MIX* opcodes should support op_sel/op_sel_hi"
href="https://bugs.llvm.org/show_bug.cgi?id=33595">33595</a>
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<th>Summary</th>
<td>[mc][gfx9] V_MAD_MIX* opcodes should support op_sel/op_sel_hi
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: AMDGPU
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>dpreobrazhensky@luxoft.com
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<p>
<div>
<pre>According with AMD doc, V_MAD_MIX* opcodes use op_sel and op_sel_hi bits to
select either 32-bit or 16-bit src. See Gfx9_Fp16_Enhancement#3_20161209AT.pdf
for details.
Current implementation hardcodes op_sel_hi=[0,0,0] for using 32-bit src
operands. op_sel modifiers are not supported.</pre>
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