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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - atomic cmpxchg release acquire doesn't reject or honor failure memory ordering"
href="https://bugs.llvm.org/show_bug.cgi?id=33332">33332</a>
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<th>Summary</th>
<td>atomic cmpxchg release acquire doesn't reject or honor failure memory ordering
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>All
</td>
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>normal
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Common Code Generator Code
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>gberry@codeaurora.org
</td>
</tr>
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
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<p>
<div>
<pre>Currently the AtomicExpandPass will lower the following IR:
define i1 @foo(i32* %obj, i32 %old, i32 %new) {
entry:
%v0 = cmpxchg weak volatile i32* %obj, i32 %old, i32 %new release acquire
%v1 = extractvalue { i32, i1 } %v0, 1
ret i1 %v1
}
to the equivalent of the following on AArch64:
ldxr w8, [x0]
cmp w8, w1
b.ne .LBB0_3
// BB#1: // %cmpxchg.trystore
stlxr w8, w2, [x0]
cbz w8, .LBB0_4
// BB#2: // %cmpxchg.failure
mov w0, wzr
ret
.LBB0_3: // %cmpxchg.nostore
clrex
mov w0, wzr
ret
.LBB0_4:
orr w0, wzr, #0x1
ret
GCC instead generates a ldaxr for the initial load, which seems more correct to
me since it is honoring the requested failure case acquire ordering. I'd like
to get other opinions on this before filing a bug.
I believe the code in AtomicExpand::expandAtomicCmpXchg() is responsible for
this discrepancy, since it only uses the failure case memory order for targets
that use fences (i.e. when TLI->shouldInsertFencesForAtomic(CI) is true).</pre>
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