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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [AMDGPU][MC][GFX9] Invalid encoding of flat_scratch* in SDWA opcodes"
href="https://bugs.llvm.org/show_bug.cgi?id=33171">33171</a>
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<th>Summary</th>
<td>[AMDGPU][MC][GFX9] Invalid encoding of flat_scratch* in SDWA opcodes
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<th>Product</th>
<td>libraries
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>All
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<th>Status</th>
<td>NEW
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<th>Severity</th>
<td>enhancement
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: AMDGPU
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>dpreobrazhensky@luxoft.com
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<th>CC</th>
<td>llvm-bugs@lists.llvm.org
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<pre>GFX9 SDWA implementation does not account for special registers like
flat_scratch which have different encoding on CI and VI+.
An example of failing test:
v_ceil_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD
src0_sel:DWORD
// CHECK: [0xf9,0x8a,0x0a,0x7e,0x66,0x06,0x86,0x06]
Assembler currently encodes flat_scratch_lo as if it were an SGPR:
[0xf9,0x8a,0x0a,0x7e,0x66,0x06,0x06,0x06]
In other words, the encoding is the same as for the following instruction:
v_ceil_f16_sdwa v5, v102 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD</pre>
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