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<base href="https://bugs.llvm.org/">
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - -verify-regalloc discovers "Instruction ending live segment on dead slot has no dead flag""
href="https://bugs.llvm.org/show_bug.cgi?id=33024">33024</a>
</td>
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<th>Summary</th>
<td>-verify-regalloc discovers "Instruction ending live segment on dead slot has no dead flag"
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
<tr>
<th>OS</th>
<td>Linux
</td>
</tr>
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<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>enhancement
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Common Code Generator Code
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>paulsson@linux.vnet.ibm.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
</tr></table>
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<pre>Created <span class=""><a href="attachment.cgi?id=18436" name="attach_18436" title="reduced testcase">attachment 18436</a> <a href="attachment.cgi?id=18436&action=edit" title="reduced testcase">[details]</a></span>
reduced testcase
With this reduced llvm-stress test case, run with
llc -mtriple=s390x-linux-gnu -mcpu=z13 -verify-regalloc -disable-lsr
-disable-machine-licm -disable-machine-dce -join-liveintervals=false -o
/dev/null ./tc_deadslot.ll
It seems that loadRegFromStackSlot() is called, and then verifier complains
that the created instruction is missing a dead-flag. I am not sure where this
should be fixed...
Output:
0B BB#0: derived from LLVM BB %BB
Live Ins: %R2L
16B %vreg5<def> = COPY %R2L; GR32Bit:%vreg5
32B %vreg10<def> = VGBM 0; VR128Bit:%vreg10
48B VST %vreg10, <fi#0>, 0, %noreg; mem:ST16[FixedStack0](align=8)
VR128Bit:%vreg10
Successors according to CFG: BB#1(?%)
64B BB#1: derived from LLVM BB %CF253
Predecessors according to CFG: BB#0 BB#1
72B %vreg11<def> = VGBM 0; VR128Bit:%vreg11
80B %vreg3<def> = COPY %vreg11; VR128Bit:%vreg3,%vreg11
96B %vreg3<def,dead,tied1> = VLVGF %vreg3<tied0>, %vreg5, %noreg,
2; VR128Bit:%vreg3 GR32Bit:%vreg5
112B ADJCALLSTACKDOWN 0
128B %vreg6<def> = LZDR; FP64Bit:%vreg6
144B %F0D<def> = COPY %vreg6; FP64Bit:%vreg6
160B %F2D<def> = COPY %vreg6; FP64Bit:%vreg6
176B CallBRASL <es:fmod>, %F0D, %F2D, <regmask %F8D %F9D %F10D %F11D
%F12D %F13D %F14D %F15D %F8S %F9S %F10S %F11S %F12S %F13S %F14S %F15S %R6D %R7D
%R8D %R9D %R10D %R11D %R12D %R13D %R14D %R15D %R6H %R7H %R8H %R9H %R10H %R11H
%R12H %R13H %R14H %R15H %R6L %R7L %R8L %R9L %R10L %R11L %R12L %R13L %R14L
%R15L>, %CC<imp-def,dead>, %F0D<imp-def>, ...
192B ADJCALLSTACKUP 0, 0
208B %vreg7<def> = COPY %F0D; VR64Bit:%vreg7
224B %vreg2<def> = VL <fi#0>, 0, %noreg;
mem:LD16[FixedStack0](align=8) VR128Bit:%vreg2
240B %vreg4<def,dead> = COPY %vreg7; VR64Bit:%vreg4,%vreg7
256B %vreg8<def> = LHIMux 0; GRX32Bit:%vreg8
272B CHIMux %vreg8, 0, %CC<imp-def>; GRX32Bit:%vreg8
288B BRC 14, 6, <BB#1>, %CC<imp-use,kill>
304B J <BB#2>
Successors according to CFG: BB#1(0x7c000000 / 0x80000000 = 96.88%)
BB#2(0x04000000 / 0x80000000 = 3.12%)
320B BB#2: derived from LLVM BB %CF258
Predecessors according to CFG: BB#1 BB#2
336B J <BB#2>
Successors according to CFG: BB#2(?%)
# End machine code for function autogen_SD9889.
*** Bad machine code: Instruction ending live segment on dead slot has no dead
flag ***
- function: autogen_SD9889
- basic block: BB#1 CF253 (0x4f45158) [64B;320B)
- instruction: 224B %vreg2<def> = VL
- liverange: [224r,224d:0) 0@224r
- v. register: %vreg2
- segment: [224r,224d:0)
LLVM ERROR: Found 1 machine code errors.</pre>
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