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<base href="https://bugs.llvm.org/">
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<body><table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - MachineCSE does not understand physical live ranges that span basic blocks"
href="https://bugs.llvm.org/show_bug.cgi?id=32538">32538</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>MachineCSE does not understand physical live ranges that span basic blocks
</td>
</tr>
<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>PC
</td>
</tr>
<tr>
<th>OS</th>
<td>Linux
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>normal
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>Common Code Generator Code
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>mattias.v.eriksson@ericsson.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
</tr></table>
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<div>
<pre>Created <span class=""><a href="attachment.cgi?id=18231" name="attach_18231" title="cse-input">attachment 18231</a> <a href="attachment.cgi?id=18231&action=edit" title="cse-input">[details]</a></span>
cse-input
Compiling the attached file like this (@297838):
llc -run-pass=machine-cse -o - cse.mir -print-after-all -print-before-all
-debug
There is a def of CPSR in BB#1 which MachineCSE removes (the first
instruction). I think this is invalid because the physical register CPSR is
live into BB#2.
I found this strange behavior when debugging an issue in my out-of-tree target
and recreated this as best as I could by modifying an existing test for ARM. It
probably makes no sense to use CPSR like I do here. But I hope it shows a bug,
or maybe you can tell me that I have misunderstood something about how physical
registers work before regalloc.
# *** IR Dump Before Machine Common Subexpression Elimination ***:
# Machine code for function spam: IsSSA, NoPHIs, TracksLiveness
Jump Tables:
jt#0: BB#2
Function Live Ins: %R0 in %vreg1, %R1 in %vreg2
BB#0: derived from LLVM BB %bb
Live Ins: %R0 %R1
%vreg2<def> = COPY %R1; tGPR:%vreg2
%vreg1<def> = COPY %R0; tGPR:%vreg1
%vreg4<def>, %CPSR<def> = tLSLri %vreg2, 2, pred:14, pred:%noreg;
tGPR:%vreg4,%vreg2
%vreg5<def>, %CPSR<def> = tADDrr %vreg1, %vreg4<kill>, pred:14,
pred:%noreg; tGPR:%vreg5,%vreg1,%vreg4
%vreg0<def,tied2>, %CPSR<def> = tADDi8 %vreg5<tied0>, 212, pred:14,
pred:%noreg; tGPR:%vreg0,%vreg5
%vreg3<def> = COPY %vreg2; tGPR:%vreg3,%vreg2
tCMPi8 %vreg2, 5, pred:14, pred:%noreg, %CPSR<imp-def>; tGPR:%vreg2
tBcc <BB#3>, pred:8, pred:%CPSR
Successors according to CFG: BB#3(0x12492492 / 0x80000000 = 14.29%)
BB#1(0x6db6db6e / 0x80000000 = 85.71%)
BB#1: derived from LLVM BB %bb
Predecessors according to CFG: BB#0
%vreg6<def>, %CPSR<def> = tLSLri %vreg3, 2, pred:14, pred:%noreg;
tGPR:%vreg6,%vreg3
%vreg7<def> = tLEApcrelJT <jt#0>, pred:14, pred:%noreg; tGPR:%vreg7
%vreg8<def> = tLDRr %vreg6<kill>, %vreg7<kill>, pred:14, pred:%noreg;
mem:LD4[JumpTable] tGPR:%vreg8,%vreg6,%vreg7
tBR_JTr %vreg8<kill>, <jt#0>; tGPR:%vreg8
Successors according to CFG: BB#2(0x80000000 / 0x80000000 = 100.00%)
BB#2: derived from LLVM BB %bb2
Live Ins: %CPSR
Predecessors according to CFG: BB#1
%vreg10<def> = COPY %CPSR; tGPR:%vreg10
BB#3: derived from LLVM BB %bb8
Predecessors according to CFG: BB#0
%vreg9<def>, %CPSR<def> = tMOVi8 1, pred:14, pred:%noreg; tGPR:%vreg9
tSTRi %vreg9<kill>, %vreg0, 0, pred:14, pred:%noreg; mem:ST4[%tmp]
tGPR:%vreg9,%vreg0
# End machine code for function spam.
Entering: bb
Entering: bb
Coalescing: %vreg3<def> = COPY %vreg2; tGPR:%vreg3,%vreg2
*** to: %vreg6<def>, %CPSR<def> = tLSLri %vreg3, 2, pred:14, pred:%noreg;
tGPR:%vreg6,%vreg3
Examining: %vreg6<def>, %CPSR<def> = tLSLri %vreg2, 2, pred:14, pred:%noreg;
tGPR:%vreg6,%vreg2
*** Found a common subexpression: %vreg4<def>, %CPSR<def> = tLSLri %vreg2, 2,
pred:14, pred:%noreg; tGPR:%vreg4,%vreg2
Entering: bb2
Exiting: bb2
Exiting: bb
Entering: bb8
Exiting: bb8
Exiting: bb
# *** IR Dump After Machine Common Subexpression Elimination ***:
# Machine code for function spam: IsSSA, NoPHIs, TracksLiveness
Jump Tables:
jt#0: BB#2
Function Live Ins: %R0 in %vreg1, %R1 in %vreg2
BB#0: derived from LLVM BB %bb
Live Ins: %R0 %R1
%vreg2<def> = COPY %R1; tGPR:%vreg2
%vreg1<def> = COPY %R0; tGPR:%vreg1
%vreg4<def>, %CPSR<def> = tLSLri %vreg2, 2, pred:14, pred:%noreg;
tGPR:%vreg4,%vreg2
%vreg5<def>, %CPSR<def> = tADDrr %vreg1, %vreg4, pred:14, pred:%noreg;
tGPR:%vreg5,%vreg1,%vreg4
%vreg0<def,tied2>, %CPSR<def> = tADDi8 %vreg5<tied0>, 212, pred:14,
pred:%noreg; tGPR:%vreg0,%vreg5
tCMPi8 %vreg2, 5, pred:14, pred:%noreg, %CPSR<imp-def>; tGPR:%vreg2
tBcc <BB#3>, pred:8, pred:%CPSR
Successors according to CFG: BB#3(0x12492492 / 0x80000000 = 14.29%)
BB#1(0x6db6db6e / 0x80000000 = 85.71%)
BB#1: derived from LLVM BB %bb
Predecessors according to CFG: BB#0
%vreg7<def> = tLEApcrelJT <jt#0>, pred:14, pred:%noreg; tGPR:%vreg7
%vreg8<def> = tLDRr %vreg4, %vreg7<kill>, pred:14, pred:%noreg;
mem:LD4[JumpTable] tGPR:%vreg8,%vreg4,%vreg7
tBR_JTr %vreg8<kill>, <jt#0>; tGPR:%vreg8
Successors according to CFG: BB#2(0x80000000 / 0x80000000 = 100.00%)
BB#2: derived from LLVM BB %bb2
Live Ins: %CPSR
Predecessors according to CFG: BB#1
%vreg10<def> = COPY %CPSR; tGPR:%vreg10
BB#3: derived from LLVM BB %bb8
Predecessors according to CFG: BB#0
%vreg9<def>, %CPSR<def> = tMOVi8 1, pred:14, pred:%noreg; tGPR:%vreg9
tSTRi %vreg9<kill>, %vreg0, 0, pred:14, pred:%noreg; mem:ST4[%tmp]
tGPR:%vreg9,%vreg0
# End machine code for function spam.
The value of CPSR that is live into BB#2 is now incorrect.
I think the error is here:
bool
MachineCSE::isPhysDefTriviallyDead(
...
if (I == E)
// Reached end of block, register is obviously dead.
return true;
When we reach the end of a block, should't we conclude that we don't know if
the value is live or not?</pre>
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