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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW - [X86] Account for domain crossing penalties in the scheduling of SSE/AVX instructions"
href="https://bugs.llvm.org/show_bug.cgi?id=32487">32487</a>
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<th>Summary</th>
<td>[X86] Account for domain crossing penalties in the scheduling of SSE/AVX instructions
</td>
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<tr>
<th>Product</th>
<td>libraries
</td>
</tr>
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<th>Version</th>
<td>trunk
</td>
</tr>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>All
</td>
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<th>Status</th>
<td>NEW
</td>
</tr>
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<th>Severity</th>
<td>enhancement
</td>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>Backend: X86
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
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<th>Reporter</th>
<td>llvm-dev@redking.me.uk
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
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<th>Blocks</th>
<td>32325
</td>
</tr></table>
<p>
<div>
<pre>X86 domain crossing penalties are a lot more complicated than we account for,
each CPUs treat instructions from the same domain quite differently. We should
be trying to better model this to allow instruction selection to better tune
for particular CPUs.</pre>
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</p>
<div id="referenced">
<hr style="border: 1px dashed #969696">
<b>Referenced Bugs:</b>
<ul>
<li>
[<a class="bz_bug_link
bz_status_NEW "
title="NEW - [META][X86] Improve implementation and use of X86 scheduler models"
href="https://bugs.llvm.org/show_bug.cgi?id=32325">Bug 32325</a>] [META][X86] Improve implementation and use of X86 scheduler models
</li>
</ul>
</div>
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