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    <head>
      <base href="https://bugs.llvm.org/">
    </head>
    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - [META][X86] Improve implementation and use of X86 scheduler models"
   href="https://bugs.llvm.org/show_bug.cgi?id=32325">32325</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>[META][X86] Improve implementation and use of X86 scheduler models
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>libraries
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>trunk
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>PC
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>Windows NT
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>enhancement
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>P
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>Backend: X86
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>unassignedbugs@nondot.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>llvm-dev@redking.me.uk
          </td>
        </tr>

        <tr>
          <th>CC</th>
          <td>andrew.v.tischenko@gmail.com, craig.topper@gmail.com, davide@freebsd.org, filcab@gmail.com, llvm-bugs@lists.llvm.org, spatel+llvm@rotateright.com
          </td>
        </tr></table>
      <p>
        <div>
        <pre>Meta ticket covering issues with the x86 scheduler models, which currently
include:

X86ScheduleAtom.td
X86SchedSandyBridge.td
X86SchedHaswell.td
X86ScheduleSLM.td
X86ScheduleBtVer2.td

Including incorrect latency/throughput values and resources.

Also covers possible improvements to how we can use the schedulers to improve
performance (e.g. use in the machine combiner for better instruction
selection).</pre>
        </div>
      </p>


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